clk/sophgo/clk-cv18xx-ip.c

605 static u8 mmux_get_parent_id(struct cv1800_clk_mmux *mmux)
607 	struct clk_hw *hw = &mmux->common.hw;
621 	struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
623 	return cv1800_clk_setbit(&mmux->common, &mmux->gate);
628 	struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
630 	cv1800_clk_clearbit(&mmux->common, &mmux->gate);
635 	struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
637 	return cv1800_clk_checkbit(&mmux->common, &mmux->gate);
643 	struct cv1800_clk_mmux *mmux = data;
647 		if (cv1800_clk_checkbit(&mmux->common, &mmux->bypass))
650 		id = mmux_get_parent_id(mmux);
653 	div_id = mmux->parent2sel[id];
658 	return div_helper_round_rate(&mmux->div[div_id],
659 				     &mmux->common.hw, parent,
666 	struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
668 	return mux_helper_determine_rate(&mmux->common, req,
669 					 mmux_round_rate, mmux);
675 	struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
679 	if (cv1800_clk_checkbit(&mmux->common, &mmux->bypass))
682 	if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel))
683 		div = &mmux->div[0];
685 		div = &mmux->div[1];
687 	val = div_helper_get_clockdiv(&mmux->common, div);
698 	struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
702 	if (cv1800_clk_checkbit(&mmux->common, &mmux->bypass))
705 	if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel))
706 		div = &mmux->div[0];
708 		div = &mmux->div[1];
713 	return div_helper_set_rate(&mmux->common, div, val);
718 	struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
723 	if (cv1800_clk_checkbit(&mmux->common, &mmux->bypass))
726 	if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel))
730 	mux = &mmux->mux[clk_sel];
732 	reg = readl(mmux->common.base + mux->reg);
734 	return mmux->sel2parent[clk_sel][cv1800_clk_regfield_get(reg, mux)];
739 	struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
743 	s8 clk_sel = mmux->parent2sel[index];
746 		cv1800_clk_setbit(&mmux->common, &mmux->bypass);
750 	cv1800_clk_clearbit(&mmux->common, &mmux->bypass);
753 		cv1800_clk_clearbit(&mmux->common, &mmux->clk_sel);
755 		cv1800_clk_setbit(&mmux->common, &mmux->clk_sel);
757 	spin_lock_irqsave(mmux->common.lock, flags);
759 	mux = &mmux->mux[clk_sel];
760 	reg = readl(mmux->common.base + mux->reg);
763 	writel(reg, mmux->common.base + mux->reg);
765 	spin_unlock_irqrestore(mmux->common.lock, flags);