Lines Matching full:xin24m
425 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
426 PNAME(mux_armclkl_p) = { "xin24m", "gpll", "lpll" };
427 PNAME(mux_armclkb01_p) = { "xin24m", "gpll", "b0pll",};
428 PNAME(mux_armclkb23_p) = { "xin24m", "gpll", "b1pll",};
430 PNAME(gpll_24m_p) = { "gpll", "xin24m" };
435 PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m"};
439 PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" };
448 PNAME(mux_24m_spll_gpll_cpll_p) = { "xin24m", "spll", "gpll", "cpll" };
449 PNAME(mux_24m_32k_p) = { "xin24m", "xin32k" };
450 PNAME(mux_24m_100m_p) = { "xin24m", "clk_100m_src" };
452 PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", "xin24m" };
453 PNAME(mux_150m_50m_24m_p) = { "clk_150m_src", "clk_50m_src", "xin24m" };
454 PNAME(mux_150m_100m_24m_p) = { "clk_150m_src", "clk_100m_src", "xin24m" };
455 PNAME(mux_200m_150m_24m_p) = { "clk_200m_src", "clk_150m_src", "xin24m" };
456 PNAME(mux_150m_100m_50m_24m_p) = { "clk_150m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
457 PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
458 PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
459 PNAME(mux_700m_400m_200m_24m_p) = { "clk_700m_src", "clk_400m_src", "clk_200m_src", "xin24m" };
460 PNAME(mux_500m_250m_100m_24m_p) = { "clk_500m_src", "clk_250m_src", "clk_100m_src", "xin24m" };
461 PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin24m" };
462 PNAME(mux_400m_200m_100m_24m_p) = { "clk_400m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
488 PNAME(clk_uart0_p) = { "clk_uart0_src", "clk_uart0_frac", "xin24m" };
489 PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
490 PNAME(clk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
491 PNAME(clk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
492 PNAME(clk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
493 PNAME(clk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
494 PNAME(clk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
495 PNAME(clk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
496 PNAME(clk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" };
497 PNAME(clk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" };
507 PNAME(pmu_300m_24m_p) = { "clk_300m_src", "xin24m" };
508 PNAME(pmu_400m_24m_p) = { "clk_400m_src", "xin24m" };
509 PNAME(pmu_100m_50m_24m_src_p) = { "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" };
510 PNAME(pmu_24m_32k_100m_src_p) = { "xin24m", "xin32k", "clk_pmu1_100m_src" };
511 PNAME(hclk_pmu1_root_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m…
512 …clk_pmu_cm0_root_p) = { "clk_pmu1_400m_src", "clk_pmu1_200m_src", "clk_pmu1_100m_src", "xin24m" };
514 PNAME(mux_24m_ppll_spll_p) = { "xin24m", "ppll", "spll" };
515 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
683 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
803 GATE(CLK_BIGCORE0_PVTM, "clk_bigcore0_pvtm", "xin24m", 0,
815 GATE(CLK_BIGCORE1_PVTM, "clk_bigcore1_pvtm", "xin24m", 0,
867 GATE(CLK_LITCORE_PVTM, "clk_litcore_pvtm", "xin24m", 0,
1001 GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0,
1008 GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0,
1015 GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0,
1052 GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0,
1151 GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0,
1153 GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0,
1155 GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0,
1157 GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0,
1339 GATE(TCLK_WDT_DDR, "tclk_wdt_ddr", "xin24m", 0,
1364 GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0,
1414 GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0,
1433 GATE(TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m", 0,
1451 GATE(TMCLK_EMMC, "tmclk_emmc", "xin24m", 0,
1529 GATE(CLK_PCIE_AUX0, "clk_pcie_aux0", "xin24m", 0,
1531 GATE(CLK_PCIE_AUX1, "clk_pcie_aux1", "xin24m", 0,
1533 GATE(CLK_PCIE_AUX2, "clk_pcie_aux2", "xin24m", 0,
1535 GATE(CLK_PCIE_AUX3, "clk_pcie_aux3", "xin24m", 0,
1537 GATE(CLK_PCIE_AUX4, "clk_pcie_aux4", "xin24m", 0,
1539 GATE(CLK_PIPEPHY0_REF, "clk_pipephy0_ref", "xin24m", 0,
1541 GATE(CLK_PIPEPHY1_REF, "clk_pipephy1_ref", "xin24m", 0,
1543 GATE(CLK_PIPEPHY2_REF, "clk_pipephy2_ref", "xin24m", 0,
1553 GATE(CLK_PMALIVE0, "clk_pmalive0", "xin24m", 0,
1555 GATE(CLK_PMALIVE1, "clk_pmalive1", "xin24m", 0,
1557 GATE(CLK_PMALIVE2, "clk_pmalive2", "xin24m", 0,
1576 GATE(SUSPEND_CLK_USB3OTG2, "suspend_clk_usb3otg2", "xin24m", 0,
1578 GATE(REF_CLK_USB3OTG2, "ref_clk_usb3otg2", "xin24m", 0,
1659 GATE(SUSPEND_CLK_USB3OTG0, "suspend_clk_usb3otg0", "xin24m", 0,
1661 GATE(REF_CLK_USB3OTG0, "ref_clk_usb3otg0", "xin24m", 0,
1663 GATE(SUSPEND_CLK_USB3OTG1, "suspend_clk_usb3otg1", "xin24m", 0,
1665 GATE(REF_CLK_USB3OTG1, "ref_clk_usb3otg1", "xin24m", 0,
1930 GATE(CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 0,
1937 GATE(CLK_EDP1_24M, "clk_edp1_24m", "xin24m", 0,
2075 GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0,
2077 GATE(CLK_HDMIHDP1, "clk_hdmihdp1", "xin24m", 0,
2125 GATE(CLK_VOP_PMU, "clk_vop_pmu", "xin24m", CLK_IGNORE_UNUSED,
2129 GATE(CLK_USBDP_PHY0_IMMORTAL, "clk_usbdp_phy0_immortal", "xin24m", CLK_IGNORE_UNUSED,
2131 GATE(CLK_USBDP_PHY1_IMMORTAL, "clk_usbdp_phy1_immortal", "xin24m", CLK_IGNORE_UNUSED,
2134 GATE(CLK_REF_PIPE_PHY0_OSC_SRC, "clk_ref_pipe_phy0_osc_src", "xin24m", 0,
2136 GATE(CLK_REF_PIPE_PHY1_OSC_SRC, "clk_ref_pipe_phy1_osc_src", "xin24m", 0,
2138 GATE(CLK_REF_PIPE_PHY2_OSC_SRC, "clk_ref_pipe_phy2_osc_src", "xin24m", 0,
2183 GATE(CLK_PMU0, "clk_pmu0", "xin24m", CLK_IS_CRITICAL,
2248 GATE(CLK_PMU1PWM_CAPTURE, "clk_pmu1pwm_capture", "xin24m", 0,