clk/rockchip/clk-rk3528.c

117 PNAME(mux_pll_p)                        = { "xin24m" };
119 PNAME(mux_24m_32k_p)                    = { "xin24m", "clk_32k" };
121 PNAME(mux_gpll_cpll_xin24m_p)           = { "gpll", "cpll", "xin24m" };
123 					    "xin24m" };
125 					    "xin24m" };
127 					    "xin24m" };
129 					    "clk_50m_src", "xin24m" };
131 					    "clk_100m_src", "xin24m" };
133 					    "clk_100m_src", "xin24m" };
135 					    "clk_100m_src", "xin24m" };
137 					    "clk_100m_src", "xin24m" };
139 					    "clk_200m_src", "xin24m" };
145 					    "xin24m", "clk_32k" };
146 PNAME(clk_ref_pcie_inner_phy_p)         = { "clk_ppll_100m_src", "xin24m" };
164 					    "xin24m" };
166 					    "xin24m" };
168 					    "xin24m" };
170 					    "xin24m" };
172 					    "xin24m" };
174 					    "xin24m" };
176 					     "xin24m" };
178 					    "xin24m" };
261 	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
299 	COMPOSITE_NOMUX(CLK_HSM, "clk_hsm", "xin24m", 0,
495 	GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0,
497 	GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0,
499 	GATE(CLK_JDBCK_DAP, "clk_jdbck_dap", "xin24m", 0,
501 	GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
504 	GATE(CLK_TIMER_ROOT, "clk_timer_root", "xin24m", 0,
559 	GATE(CLK_REFOUT, "clk_refout", "xin24m", 0,
561 	COMPOSITE_NOMUX(CLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
565 	COMPOSITE_FRAC(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", 0,
573 	GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "xin24m", CLK_IGNORE_UNUSED,
608 	GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
730 	GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0,
838 	GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
841 	GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0,
843 	GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0,
845 	GATE(CLK_REF_USBPHY, "clk_ref_usbphy", "xin24m", 0,
847 	GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0,
875 	GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
877 	GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0,
879 	GATE(CLK_SUSPEND_USB3OTG, "clk_suspend_usb3otg", "xin24m", 0,
881 	GATE(CLK_PCIE_AUX, "clk_pcie_aux", "xin24m", 0,
883 	GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0,
885 	GATE(CLK_REF_USB3OTG, "clk_ref_usb3otg", "xin24m", 0,
1012 	COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0,
1015 	COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
1018 	COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0,