56 	unsigned int mult;  in cpg_pll_clk_recalc_rate()  local
58 	mult = FIELD_GET(CPG_PLLnCR_STC_MASK, readl(pll_clk->pllcr_reg)) + 1;  in cpg_pll_clk_recalc_rate()
60 	return parent_rate * mult * pll_clk->fixed_mult;  in cpg_pll_clk_recalc_rate()
67 	unsigned int min_mult, max_mult, mult;  in cpg_pll_clk_determine_rate()  local
76 	mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate);  in cpg_pll_clk_determine_rate()
77 	mult = clamp(mult, min_mult, max_mult);  in cpg_pll_clk_determine_rate()
79 	req->rate = prate * mult;  in cpg_pll_clk_determine_rate()
87 	unsigned int mult, i;  in cpg_pll_clk_set_rate()  local
90 	mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult);  in cpg_pll_clk_set_rate()
91 	mult = clamp(mult, 1U, 128U);  in cpg_pll_clk_set_rate()
95 	val |= FIELD_PREP(CPG_PLLnCR_STC_MASK, mult - 1);  in cpg_pll_clk_set_rate()
117 						unsigned int mult,  in cpg_pll_clk_register()  argument
138 	pll_clk->fixed_mult = mult;	/* PLL refclk x (setting + 1) x mult */  in cpg_pll_clk_register()
177 	unsigned int mult = 32 - field_get(zclk->mask, readl(zclk->reg));  in cpg_z_clk_recalc_rate()  local
179 	return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,  in cpg_z_clk_recalc_rate()
187 	unsigned int min_mult, max_mult, mult;  in cpg_z_clk_determine_rate()  local
207 	mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate);  in cpg_z_clk_determine_rate()
208 	mult = clamp(mult, min_mult, max_mult);  in cpg_z_clk_determine_rate()
210 	req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32);  in cpg_z_clk_determine_rate()
218 	unsigned int mult;  in cpg_z_clk_set_rate()  local
221 	mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,  in cpg_z_clk_set_rate()
223 	mult = clamp(mult, 1U, 32U);  in cpg_z_clk_set_rate()
229 		       field_prep(zclk->mask, 32 - mult));  in cpg_z_clk_set_rate()
349 	unsigned int mult = 1;  in rcar_gen3_cpg_clk_register()  local
372 		mult = cpg_pll_config->pll1_mult;  in rcar_gen3_cpg_clk_register()
386 		mult = cpg_pll_config->pll3_mult;  in rcar_gen3_cpg_clk_register()
398 		mult = (((value >> 24) & 0x7f) + 1) * 2;  in rcar_gen3_cpg_clk_register()
453 		mult = 1;  in rcar_gen3_cpg_clk_register()
534 					 __clk_get_name(parent), 0, mult, div);  in rcar_gen3_cpg_clk_register()