clk/renesas/r9a08g045-cpg.c

19 #define G3S_CPG_PL2_DDIV		(0x204)
20 #define G3S_CPG_SDHI_DDIV		(0x218)
21 #define G3S_CPG_PLL_DSEL		(0x240)
22 #define G3S_CPG_SDHI_DSEL		(0x244)
23 #define G3S_CLKDIVSTATUS		(0x280)
24 #define G3S_CLKSELSTATUS		(0x284)
28 #define G3S_DIV_SDHI0		DDIV_PACK(G3S_CPG_SDHI_DDIV, 0, 1)
33 #define G3S_DIVPL1A_STS		DDIV_PACK(G3S_CLKDIVSTATUS, 0, 1)
49 #define G3S_SEL_SDHI0		SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 0, 2)
101 	{ 0, 1 },
103 	{ 0, 0 },
107 	{ 0, 1 },
111 	{ 0, 0 },
115 	{ 0, 1 },
120 	{ 0, 0 },
128 static const u32 mtable_sd[] = { 0, 2, 3 };
129 static const u32 mtable_pll4[] = { 0, 1 };
137 	DEF_G3S_PLL(".pll1", CLK_PLL1, CLK_EXTAL, G3S_PLL146_CONF(0x4, 0x8, 0x100),
152 		   mtable_sd, 0, NULL),
154 		   mtable_sd, 0, NULL),
156 		   mtable_sd, 0, NULL),
162 		    0, 0, 0, NULL),
164 		    dtable_1_32, 0, 0, 0, NULL),
179 		    dtable_1_32, 0, 0, 0, NULL),
182 		    dtable_1_32, 0, 0, 0, NULL),
184 		    dtable_1_32, 0, 0, 0, NULL),
195 	DEF_MOD("gic_gicclk",		R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0,
197 	DEF_MOD("ia55_pclk",		R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0,
199 	DEF_MOD("ia55_clk",		R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1,
201 	DEF_MOD("dmac_aclk",		R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0,
203 	DEF_MOD("dmac_pclk",		R9A08G045_DMAC_PCLK, CLK_P3_DIV2, 0x52c, 1,
205 	DEF_MOD("wdt0_pclk",		R9A08G045_WDT0_PCLK, R9A08G045_CLK_P0, 0x548, 0,
206 					MSTOP(BUS_REG0, BIT(0))),
207 	DEF_MOD("wdt0_clk",		R9A08G045_WDT0_CLK, R9A08G045_OSCCLK, 0x548, 1,
208 					MSTOP(BUS_REG0, BIT(0))),
209 	DEF_MOD("sdhi0_imclk",		R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0,
210 					MSTOP(BUS_PERI_COM, BIT(0))),
211 	DEF_MOD("sdhi0_imclk2",		R9A08G045_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1,
212 					MSTOP(BUS_PERI_COM, BIT(0))),
213 	DEF_MOD("sdhi0_clk_hs",		R9A08G045_SDHI0_CLK_HS, R9A08G045_CLK_SD0, 0x554, 2,
214 					MSTOP(BUS_PERI_COM, BIT(0))),
215 	DEF_MOD("sdhi0_aclk",		R9A08G045_SDHI0_ACLK, R9A08G045_CLK_P1, 0x554, 3,
216 					MSTOP(BUS_PERI_COM, BIT(0))),
217 	DEF_MOD("sdhi1_imclk",		R9A08G045_SDHI1_IMCLK, CLK_SD1_DIV4, 0x554, 4,
219 	DEF_MOD("sdhi1_imclk2",		R9A08G045_SDHI1_IMCLK2, CLK_SD1_DIV4, 0x554, 5,
221 	DEF_MOD("sdhi1_clk_hs",		R9A08G045_SDHI1_CLK_HS, R9A08G045_CLK_SD1, 0x554, 6,
223 	DEF_MOD("sdhi1_aclk",		R9A08G045_SDHI1_ACLK, R9A08G045_CLK_P1, 0x554, 7,
225 	DEF_MOD("sdhi2_imclk",		R9A08G045_SDHI2_IMCLK, CLK_SD2_DIV4, 0x554, 8,
227 	DEF_MOD("sdhi2_imclk2",		R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9,
229 	DEF_MOD("sdhi2_clk_hs",		R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10,
231 	DEF_MOD("sdhi2_aclk",		R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11,
233 	DEF_MOD("ssi0_pclk2",		R9A08G045_SSI0_PCLK2, R9A08G045_CLK_P0, 0x570, 0,
235 	DEF_MOD("ssi0_sfr",		R9A08G045_SSI0_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 1,
237 	DEF_MOD("ssi1_pclk2",		R9A08G045_SSI1_PCLK2, R9A08G045_CLK_P0, 0x570, 2,
239 	DEF_MOD("ssi1_sfr",		R9A08G045_SSI1_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 3,
241 	DEF_MOD("ssi2_pclk2",		R9A08G045_SSI2_PCLK2, R9A08G045_CLK_P0, 0x570, 4,
243 	DEF_MOD("ssi2_sfr",		R9A08G045_SSI2_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 5,
245 	DEF_MOD("ssi3_pclk2",		R9A08G045_SSI3_PCLK2, R9A08G045_CLK_P0, 0x570, 6,
247 	DEF_MOD("ssi3_sfr",		R9A08G045_SSI3_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 7,
249 	DEF_MOD("usb0_host",		R9A08G045_USB_U2H0_HCLK, R9A08G045_CLK_P1, 0x578, 0,
251 	DEF_MOD("usb1_host",		R9A08G045_USB_U2H1_HCLK, R9A08G045_CLK_P1, 0x578, 1,
253 	DEF_MOD("usb0_func",		R9A08G045_USB_U2P_EXR_CPUCLK, R9A08G045_CLK_P1, 0x578, 2,
255 	DEF_MOD("usb_pclk",		R9A08G045_USB_PCLK, R9A08G045_CLK_P1, 0x578, 3,
257 	DEF_COUPLED("eth0_axi",		R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0,
259 	DEF_COUPLED("eth0_chi",		R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 0,
261 	DEF_MOD("eth0_refclk",		R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8, 0),
262 	DEF_COUPLED("eth1_axi",		R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1,
264 	DEF_COUPLED("eth1_chi",		R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1,
266 	DEF_MOD("eth1_refclk",		R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9, 0),
267 	DEF_MOD("i2c0_pclk",		R9A08G045_I2C0_PCLK, R9A08G045_CLK_P0, 0x580, 0,
269 	DEF_MOD("i2c1_pclk",		R9A08G045_I2C1_PCLK, R9A08G045_CLK_P0, 0x580, 1,
271 	DEF_MOD("i2c2_pclk",		R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2,
273 	DEF_MOD("i2c3_pclk",		R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3,
275 	DEF_MOD("scif0_clk_pck",	R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0,
277 	DEF_MOD("scif1_clk_pck",	R9A08G045_SCIF1_CLK_PCK, R9A08G045_CLK_P0, 0x584, 1,
279 	DEF_MOD("scif2_clk_pck",	R9A08G045_SCIF2_CLK_PCK, R9A08G045_CLK_P0, 0x584, 2,
281 	DEF_MOD("scif3_clk_pck",	R9A08G045_SCIF3_CLK_PCK, R9A08G045_CLK_P0, 0x584, 3,
283 	DEF_MOD("scif4_clk_pck",	R9A08G045_SCIF4_CLK_PCK, R9A08G045_CLK_P0, 0x584, 4,
285 	DEF_MOD("scif5_clk_pck",	R9A08G045_SCIF5_CLK_PCK, R9A08G045_CLK_P0, 0x584, 5,
287 	DEF_MOD("gpio_hclk",		R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0, 0),
288 	DEF_MOD("adc_adclk",		R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0,
290 	DEF_MOD("adc_pclk",		R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1,
292 	DEF_MOD("tsu_pclk",		R9A08G045_TSU_PCLK, R9A08G045_CLK_TSU, 0x5ac, 0,
294 	DEF_MOD("vbat_bclk",		R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0,
299 	DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0),
300 	DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1),
301 	DEF_RST(R9A08G045_IA55_RESETN, 0x818, 0),
302 	DEF_RST(R9A08G045_DMAC_ARESETN, 0x82c, 0),
303 	DEF_RST(R9A08G045_DMAC_RST_ASYNC, 0x82c, 1),
304 	DEF_RST(R9A08G045_WDT0_PRESETN, 0x848, 0),
305 	DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0),
306 	DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1),
307 	DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),
308 	DEF_RST(R9A08G045_SSI0_RST_M2_REG, 0x870, 0),
309 	DEF_RST(R9A08G045_SSI1_RST_M2_REG, 0x870, 1),
310 	DEF_RST(R9A08G045_SSI2_RST_M2_REG, 0x870, 2),
311 	DEF_RST(R9A08G045_SSI3_RST_M2_REG, 0x870, 3),
312 	DEF_RST(R9A08G045_USB_U2H0_HRESETN, 0x878, 0),
313 	DEF_RST(R9A08G045_USB_U2H1_HRESETN, 0x878, 1),
314 	DEF_RST(R9A08G045_USB_U2P_EXL_SYSRST, 0x878, 2),
315 	DEF_RST(R9A08G045_USB_PRESETN, 0x878, 3),
316 	DEF_RST(R9A08G045_ETH0_RST_HW_N, 0x87c, 0),
317 	DEF_RST(R9A08G045_ETH1_RST_HW_N, 0x87c, 1),
318 	DEF_RST(R9A08G045_I2C0_MRST, 0x880, 0),
319 	DEF_RST(R9A08G045_I2C1_MRST, 0x880, 1),
320 	DEF_RST(R9A08G045_I2C2_MRST, 0x880, 2),
321 	DEF_RST(R9A08G045_I2C3_MRST, 0x880, 3),
322 	DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0),
323 	DEF_RST(R9A08G045_SCIF1_RST_SYSTEM_N, 0x884, 1),
324 	DEF_RST(R9A08G045_SCIF2_RST_SYSTEM_N, 0x884, 2),
325 	DEF_RST(R9A08G045_SCIF3_RST_SYSTEM_N, 0x884, 3),
326 	DEF_RST(R9A08G045_SCIF4_RST_SYSTEM_N, 0x884, 4),
327 	DEF_RST(R9A08G045_SCIF5_RST_SYSTEM_N, 0x884, 5),
328 	DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0),
329 	DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1),
330 	DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2),
331 	DEF_RST(R9A08G045_ADC_PRESETN, 0x8a8, 0),
332 	DEF_RST(R9A08G045_ADC_ADRST_N, 0x8a8, 1),
333 	DEF_RST(R9A08G045_TSU_PRESETN, 0x8ac, 0),
334 	DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0),