clk/mxs/clk-ssp.c

24 	u32 clock_divide, clock_rate;
29 	for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) {
30 		clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
36 	if (clock_divide > 254) {
42 	ssp_sck = ssp_clk / clock_divide / (1 + clock_rate);
46 	val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE);
53 		"%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
54 		__func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate);