Lines Matching refs:hw
173 .hw.init = &(struct clk_init_data){
190 .hw.init = &(struct clk_init_data){
194 &g12a_fixed_pll_dco.hw
238 .hw.init = &(struct clk_init_data){
257 .hw.init = &(struct clk_init_data){
261 &g12a_sys_pll_dco.hw
297 .hw.init = &(struct clk_init_data){
316 .hw.init = &(struct clk_init_data){
320 &g12b_sys1_pll_dco.hw
332 .hw.init = &(struct clk_init_data) {
335 .parent_hws = (const struct clk_hw *[]) { &g12a_sys_pll.hw },
349 .hw.init = &(struct clk_init_data) {
353 &g12b_sys1_pll.hw
366 .hw.init = &(struct clk_init_data){
370 &g12a_sys_pll_div16_en.hw
379 .hw.init = &(struct clk_init_data){
383 &g12b_sys1_pll_div16_en.hw
392 .hw.init = &(struct clk_init_data){
395 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
405 .hw.init = &(struct clk_init_data){
409 &g12a_fclk_div2_div.hw
429 .hw.init = &(struct clk_init_data){
432 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
442 .hw.init = &(struct clk_init_data){
446 &g12a_fclk_div3_div.hw
470 .hw.init = &(struct clk_init_data){
475 { .hw = &g12a_fclk_div2.hw },
476 { .hw = &g12a_fclk_div3.hw },
490 .hw.init = &(struct clk_init_data){
495 { .hw = &g12a_fclk_div2.hw },
496 { .hw = &g12a_fclk_div3.hw },
518 .hw.init = &(struct clk_init_data){
522 &g12a_cpu_clk_premux0.hw
537 .hw.init = &(struct clk_init_data){
541 &g12a_cpu_clk_premux0.hw,
542 &g12a_cpu_clk_mux0_div.hw,
556 .hw.init = &(struct clk_init_data){
560 &g12a_cpu_clk_premux1.hw
573 .hw.init = &(struct clk_init_data){
577 &g12a_cpu_clk_premux1.hw,
578 &g12a_cpu_clk_mux1_div.hw,
594 .hw.init = &(struct clk_init_data){
598 &g12a_cpu_clk_postmux0.hw,
599 &g12a_cpu_clk_postmux1.hw,
614 .hw.init = &(struct clk_init_data){
618 &g12a_cpu_clk_dyn.hw,
619 &g12a_sys_pll.hw,
634 .hw.init = &(struct clk_init_data){
638 &g12a_cpu_clk_dyn.hw,
639 &g12b_sys1_pll.hw
654 .hw.init = &(struct clk_init_data){
659 { .hw = &g12a_fclk_div2.hw },
660 { .hw = &g12a_fclk_div3.hw },
681 .hw.init = &(struct clk_init_data){
685 &g12b_cpub_clk_premux0.hw
700 .hw.init = &(struct clk_init_data){
704 &g12b_cpub_clk_premux0.hw,
705 &g12b_cpub_clk_mux0_div.hw
719 .hw.init = &(struct clk_init_data){
724 { .hw = &g12a_fclk_div2.hw },
725 { .hw = &g12a_fclk_div3.hw },
740 .hw.init = &(struct clk_init_data){
744 &g12b_cpub_clk_premux1.hw
757 .hw.init = &(struct clk_init_data){
761 &g12b_cpub_clk_premux1.hw,
762 &g12b_cpub_clk_mux1_div.hw
778 .hw.init = &(struct clk_init_data){
782 &g12b_cpub_clk_postmux0.hw,
783 &g12b_cpub_clk_postmux1.hw
798 .hw.init = &(struct clk_init_data){
802 &g12b_cpub_clk_dyn.hw,
803 &g12a_sys_pll.hw
819 .hw.init = &(struct clk_init_data){
824 { .hw = &g12a_fclk_div2.hw },
825 { .hw = &g12a_fclk_div3.hw },
826 { .hw = &sm1_gp1_pll.hw },
839 .hw.init = &(struct clk_init_data){
844 { .hw = &g12a_fclk_div2.hw },
845 { .hw = &g12a_fclk_div3.hw },
846 { .hw = &sm1_gp1_pll.hw },
859 .hw.init = &(struct clk_init_data){
863 &sm1_dsu_clk_premux0.hw
876 .hw.init = &(struct clk_init_data){
880 &sm1_dsu_clk_premux0.hw,
881 &sm1_dsu_clk_mux0_div.hw,
894 .hw.init = &(struct clk_init_data){
898 &sm1_dsu_clk_premux1.hw
911 .hw.init = &(struct clk_init_data){
915 &sm1_dsu_clk_premux1.hw,
916 &sm1_dsu_clk_mux1_div.hw,
929 .hw.init = &(struct clk_init_data){
933 &sm1_dsu_clk_postmux0.hw,
934 &sm1_dsu_clk_postmux1.hw,
947 .hw.init = &(struct clk_init_data){
951 &sm1_dsu_clk_dyn.hw,
952 &g12a_sys_pll.hw,
965 .hw.init = &(struct clk_init_data){
969 &g12a_cpu_clk.hw,
983 .hw.init = &(struct clk_init_data){
987 &g12a_cpu_clk.hw,
1001 .hw.init = &(struct clk_init_data){
1005 &g12a_cpu_clk.hw,
1019 .hw.init = &(struct clk_init_data){
1023 &g12a_cpu_clk.hw,
1024 &sm1_dsu_final_clk.hw,
1136 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1137 .cpu_clk_postmux0 = &g12a_cpu_clk_postmux0.hw,
1138 .cpu_clk_postmux1 = &g12a_cpu_clk_postmux1.hw,
1139 .cpu_clk_premux1 = &g12a_cpu_clk_premux1.hw,
1144 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1145 .cpu_clk_postmux0 = &g12b_cpub_clk_postmux0.hw,
1146 .cpu_clk_postmux1 = &g12b_cpub_clk_postmux1.hw,
1147 .cpu_clk_premux1 = &g12b_cpub_clk_premux1.hw,
1219 .sys_pll = &g12a_sys_pll.hw,
1220 .cpu_clk = &g12a_cpu_clk.hw,
1221 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1227 .sys_pll = &g12b_sys1_pll.hw,
1228 .cpu_clk = &g12b_cpu_clk.hw,
1229 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1235 .sys_pll = &g12a_sys_pll.hw,
1236 .cpu_clk = &g12b_cpub_clk.hw,
1237 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1246 .hw.init = &(struct clk_init_data) {
1275 .hw.init = &(struct clk_init_data) {
1279 &g12b_cpub_clk.hw
1292 .hw.init = &(struct clk_init_data){
1296 &g12a_cpu_clk_div16_en.hw
1305 .hw.init = &(struct clk_init_data){
1309 &g12b_cpub_clk_div16_en.hw
1322 .hw.init = &(struct clk_init_data){
1338 .hw.init = &(struct clk_init_data) {
1342 &g12a_cpu_clk_apb_div.hw
1359 .hw.init = &(struct clk_init_data){
1375 .hw.init = &(struct clk_init_data) {
1379 &g12a_cpu_clk_atb_div.hw
1396 .hw.init = &(struct clk_init_data){
1412 .hw.init = &(struct clk_init_data) {
1416 &g12a_cpu_clk_axi_div.hw
1433 .hw.init = &(struct clk_init_data){
1449 .hw.init = &(struct clk_init_data) {
1453 &g12a_cpu_clk_trace_div.hw
1466 .hw.init = &(struct clk_init_data){
1470 &g12b_cpub_clk.hw
1479 .hw.init = &(struct clk_init_data){
1483 &g12b_cpub_clk.hw
1492 .hw.init = &(struct clk_init_data){
1496 &g12b_cpub_clk.hw
1505 .hw.init = &(struct clk_init_data){
1509 &g12b_cpub_clk.hw
1518 .hw.init = &(struct clk_init_data){
1522 &g12b_cpub_clk.hw
1531 .hw.init = &(struct clk_init_data){
1535 &g12b_cpub_clk.hw
1544 .hw.init = &(struct clk_init_data){
1548 &g12b_cpub_clk.hw
1562 .hw.init = &(struct clk_init_data){
1566 &g12b_cpub_clk_div2.hw,
1567 &g12b_cpub_clk_div3.hw,
1568 &g12b_cpub_clk_div4.hw,
1569 &g12b_cpub_clk_div5.hw,
1570 &g12b_cpub_clk_div6.hw,
1571 &g12b_cpub_clk_div7.hw,
1572 &g12b_cpub_clk_div8.hw
1584 .hw.init = &(struct clk_init_data) {
1588 &g12b_cpub_clk_apb_sel.hw
1605 .hw.init = &(struct clk_init_data){
1609 &g12b_cpub_clk_div2.hw,
1610 &g12b_cpub_clk_div3.hw,
1611 &g12b_cpub_clk_div4.hw,
1612 &g12b_cpub_clk_div5.hw,
1613 &g12b_cpub_clk_div6.hw,
1614 &g12b_cpub_clk_div7.hw,
1615 &g12b_cpub_clk_div8.hw
1627 .hw.init = &(struct clk_init_data) {
1631 &g12b_cpub_clk_atb_sel.hw
1648 .hw.init = &(struct clk_init_data){
1652 &g12b_cpub_clk_div2.hw,
1653 &g12b_cpub_clk_div3.hw,
1654 &g12b_cpub_clk_div4.hw,
1655 &g12b_cpub_clk_div5.hw,
1656 &g12b_cpub_clk_div6.hw,
1657 &g12b_cpub_clk_div7.hw,
1658 &g12b_cpub_clk_div8.hw
1670 .hw.init = &(struct clk_init_data) {
1674 &g12b_cpub_clk_axi_sel.hw
1691 .hw.init = &(struct clk_init_data){
1695 &g12b_cpub_clk_div2.hw,
1696 &g12b_cpub_clk_div3.hw,
1697 &g12b_cpub_clk_div4.hw,
1698 &g12b_cpub_clk_div5.hw,
1699 &g12b_cpub_clk_div6.hw,
1700 &g12b_cpub_clk_div7.hw,
1701 &g12b_cpub_clk_div8.hw
1713 .hw.init = &(struct clk_init_data) {
1717 &g12b_cpub_clk_trace_sel.hw
1780 .hw.init = &(struct clk_init_data){
1798 .hw.init = &(struct clk_init_data){
1802 &g12a_gp0_pll_dco.hw
1842 .hw.init = &(struct clk_init_data){
1862 .hw.init = &(struct clk_init_data){
1866 &sm1_gp1_pll_dco.hw
1921 .hw.init = &(struct clk_init_data){
1939 .hw.init = &(struct clk_init_data){
1943 &g12a_hifi_pll_dco.hw
2012 .hw.init = &(struct clk_init_data){
2025 .hw.init = &(struct clk_init_data){
2029 &g12a_pcie_pll_dco.hw
2045 .hw.init = &(struct clk_init_data){
2049 &g12a_pcie_pll_dco_div2.hw
2059 .hw.init = &(struct clk_init_data){
2063 &g12a_pcie_pll_od.hw
2103 .hw.init = &(struct clk_init_data){
2125 .hw.init = &(struct clk_init_data){
2129 &g12a_hdmi_pll_dco.hw
2143 .hw.init = &(struct clk_init_data){
2147 &g12a_hdmi_pll_od.hw
2161 .hw.init = &(struct clk_init_data){
2165 &g12a_hdmi_pll_od2.hw
2175 .hw.init = &(struct clk_init_data){
2178 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2188 .hw.init = &(struct clk_init_data){
2192 &g12a_fclk_div4_div.hw
2201 .hw.init = &(struct clk_init_data){
2204 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2214 .hw.init = &(struct clk_init_data){
2218 &g12a_fclk_div5_div.hw
2227 .hw.init = &(struct clk_init_data){
2230 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2240 .hw.init = &(struct clk_init_data){
2244 &g12a_fclk_div7_div.hw
2253 .hw.init = &(struct clk_init_data){
2257 &g12a_fixed_pll_dco.hw
2268 .hw.init = &(struct clk_init_data){
2272 &g12a_fclk_div2p5_div.hw
2281 .hw.init = &(struct clk_init_data){
2285 &g12a_fixed_pll_dco.hw
2297 .hw.init = &(struct clk_init_data){
2302 { .hw = &g12a_mpll_50m_div.hw },
2311 .hw.init = &(struct clk_init_data){
2315 &g12a_fixed_pll_dco.hw
2350 .hw.init = &(struct clk_init_data){
2354 &g12a_mpll_prediv.hw
2365 .hw.init = &(struct clk_init_data){
2368 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll0_div.hw },
2403 .hw.init = &(struct clk_init_data){
2407 &g12a_mpll_prediv.hw
2418 .hw.init = &(struct clk_init_data){
2421 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll1_div.hw },
2456 .hw.init = &(struct clk_init_data){
2460 &g12a_mpll_prediv.hw
2471 .hw.init = &(struct clk_init_data){
2474 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll2_div.hw },
2509 .hw.init = &(struct clk_init_data){
2513 &g12a_mpll_prediv.hw
2524 .hw.init = &(struct clk_init_data){
2527 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll3_div.hw },
2536 { .hw = &g12a_fclk_div7.hw },
2537 { .hw = &g12a_mpll1.hw },
2538 { .hw = &g12a_mpll2.hw },
2539 { .hw = &g12a_fclk_div4.hw },
2540 { .hw = &g12a_fclk_div3.hw },
2541 { .hw = &g12a_fclk_div5.hw },
2551 .hw.init = &(struct clk_init_data){
2565 .hw.init = &(struct clk_init_data){
2569 &g12a_mpeg_clk_sel.hw
2581 .hw.init = &(struct clk_init_data){
2585 &g12a_mpeg_clk_div.hw
2594 { .hw = &g12a_fclk_div2.hw },
2595 { .hw = &g12a_fclk_div3.hw },
2596 { .hw = &g12a_fclk_div5.hw },
2597 { .hw = &g12a_fclk_div7.hw },
2613 .hw.init = &(struct clk_init_data) {
2628 .hw.init = &(struct clk_init_data) {
2632 &g12a_sd_emmc_a_clk0_sel.hw
2644 .hw.init = &(struct clk_init_data){
2648 &g12a_sd_emmc_a_clk0_div.hw
2662 .hw.init = &(struct clk_init_data) {
2677 .hw.init = &(struct clk_init_data) {
2681 &g12a_sd_emmc_b_clk0_sel.hw
2693 .hw.init = &(struct clk_init_data){
2697 &g12a_sd_emmc_b_clk0_div.hw
2711 .hw.init = &(struct clk_init_data) {
2726 .hw.init = &(struct clk_init_data) {
2730 &g12a_sd_emmc_c_clk0_sel.hw
2742 .hw.init = &(struct clk_init_data){
2746 &g12a_sd_emmc_c_clk0_div.hw
2768 .hw.init = &(struct clk_init_data) {
2771 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_pll.hw },
2778 &g12a_vid_pll_div.hw,
2779 &g12a_hdmi_pll.hw,
2788 .hw.init = &(struct clk_init_data){
2806 .hw.init = &(struct clk_init_data) {
2810 &g12a_vid_pll_sel.hw
2820 &g12a_fclk_div3.hw,
2821 &g12a_fclk_div4.hw,
2822 &g12a_fclk_div5.hw,
2823 &g12a_fclk_div7.hw,
2824 &g12a_mpll1.hw,
2825 &g12a_vid_pll.hw,
2826 &g12a_hifi_pll.hw,
2827 &g12a_gp0_pll.hw,
2836 .hw.init = &(struct clk_init_data){
2851 .hw.init = &(struct clk_init_data){
2854 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_sel.hw },
2865 .hw.init = &(struct clk_init_data) {
2868 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_div.hw },
2880 .hw.init = &(struct clk_init_data){
2895 .hw.init = &(struct clk_init_data){
2898 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_sel.hw },
2909 .hw.init = &(struct clk_init_data) {
2912 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_div.hw },
2924 .hw.init = &(struct clk_init_data){
2932 &g12a_vpu_0.hw,
2933 &g12a_vpu_1.hw,
2943 &g12a_fclk_div2p5.hw,
2944 &g12a_fclk_div3.hw,
2945 &g12a_fclk_div4.hw,
2946 &g12a_fclk_div5.hw,
2947 &g12a_fclk_div7.hw,
2948 &g12a_hifi_pll.hw,
2949 &g12a_gp0_pll.hw,
2959 .hw.init = &(struct clk_init_data){
2975 .hw.init = &(struct clk_init_data){
2979 &g12a_vdec_1_sel.hw
2991 .hw.init = &(struct clk_init_data) {
2995 &g12a_vdec_1_div.hw
3009 .hw.init = &(struct clk_init_data){
3025 .hw.init = &(struct clk_init_data){
3029 &g12a_vdec_hevcf_sel.hw
3041 .hw.init = &(struct clk_init_data) {
3045 &g12a_vdec_hevcf_div.hw
3059 .hw.init = &(struct clk_init_data){
3075 .hw.init = &(struct clk_init_data){
3079 &g12a_vdec_hevc_sel.hw
3091 .hw.init = &(struct clk_init_data) {
3095 &g12a_vdec_hevc_div.hw
3105 &g12a_fclk_div4.hw,
3106 &g12a_fclk_div3.hw,
3107 &g12a_fclk_div5.hw,
3108 &g12a_fclk_div7.hw,
3109 &g12a_mpll1.hw,
3110 &g12a_vid_pll.hw,
3111 &g12a_mpll2.hw,
3112 &g12a_fclk_div2p5.hw,
3121 .hw.init = &(struct clk_init_data){
3136 .hw.init = &(struct clk_init_data){
3140 &g12a_vapb_0_sel.hw
3152 .hw.init = &(struct clk_init_data) {
3156 &g12a_vapb_0_div.hw
3169 .hw.init = &(struct clk_init_data){
3184 .hw.init = &(struct clk_init_data){
3188 &g12a_vapb_1_sel.hw
3200 .hw.init = &(struct clk_init_data) {
3204 &g12a_vapb_1_div.hw
3217 .hw.init = &(struct clk_init_data){
3225 &g12a_vapb_0.hw,
3226 &g12a_vapb_1.hw,
3238 .hw.init = &(struct clk_init_data) {
3241 .parent_hws = (const struct clk_hw *[]) { &g12a_vapb_sel.hw },
3248 &g12a_vid_pll.hw,
3249 &g12a_gp0_pll.hw,
3250 &g12a_hifi_pll.hw,
3251 &g12a_mpll1.hw,
3252 &g12a_fclk_div3.hw,
3253 &g12a_fclk_div4.hw,
3254 &g12a_fclk_div5.hw,
3255 &g12a_fclk_div7.hw,
3264 .hw.init = &(struct clk_init_data){
3279 .hw.init = &(struct clk_init_data){
3293 .hw.init = &(struct clk_init_data) {
3296 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_sel.hw },
3307 .hw.init = &(struct clk_init_data) {
3310 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
3321 .hw.init = &(struct clk_init_data){
3325 &g12a_vclk_input.hw
3351 .hw.init = &(struct clk_init_data){
3355 &g12a_vclk2_input.hw
3367 .hw.init = &(struct clk_init_data) {
3370 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_div.hw },
3389 .hw.init = &(struct clk_init_data) {
3392 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
3403 .hw.init = &(struct clk_init_data) {
3406 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3417 .hw.init = &(struct clk_init_data) {
3420 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3431 .hw.init = &(struct clk_init_data) {
3434 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3445 .hw.init = &(struct clk_init_data) {
3448 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3459 .hw.init = &(struct clk_init_data) {
3462 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3473 .hw.init = &(struct clk_init_data) {
3476 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3487 .hw.init = &(struct clk_init_data) {
3490 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3501 .hw.init = &(struct clk_init_data) {
3504 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3515 .hw.init = &(struct clk_init_data) {
3518 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3529 .hw.init = &(struct clk_init_data) {
3532 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3541 .hw.init = &(struct clk_init_data){
3545 &g12a_vclk_div2_en.hw
3554 .hw.init = &(struct clk_init_data){
3558 &g12a_vclk_div4_en.hw
3567 .hw.init = &(struct clk_init_data){
3571 &g12a_vclk_div6_en.hw
3580 .hw.init = &(struct clk_init_data){
3584 &g12a_vclk_div12_en.hw
3593 .hw.init = &(struct clk_init_data){
3597 &g12a_vclk2_div2_en.hw
3607 .hw.init = &(struct clk_init_data){
3611 &g12a_vclk2_div4_en.hw
3621 .hw.init = &(struct clk_init_data){
3625 &g12a_vclk2_div6_en.hw
3635 .hw.init = &(struct clk_init_data){
3639 &g12a_vclk2_div12_en.hw
3648 &g12a_vclk_div1.hw,
3649 &g12a_vclk_div2.hw,
3650 &g12a_vclk_div4.hw,
3651 &g12a_vclk_div6.hw,
3652 &g12a_vclk_div12.hw,
3653 &g12a_vclk2_div1.hw,
3654 &g12a_vclk2_div2.hw,
3655 &g12a_vclk2_div4.hw,
3656 &g12a_vclk2_div6.hw,
3657 &g12a_vclk2_div12.hw,
3667 .hw.init = &(struct clk_init_data){
3683 .hw.init = &(struct clk_init_data){
3699 .hw.init = &(struct clk_init_data){
3715 .hw.init = &(struct clk_init_data){
3727 &g12a_vclk_div1.hw,
3728 &g12a_vclk_div2.hw,
3729 &g12a_vclk_div4.hw,
3730 &g12a_vclk_div6.hw,
3731 &g12a_vclk_div12.hw,
3732 &g12a_vclk2_div1.hw,
3733 &g12a_vclk2_div2.hw,
3734 &g12a_vclk2_div4.hw,
3735 &g12a_vclk2_div6.hw,
3736 &g12a_vclk2_div12.hw,
3746 .hw.init = &(struct clk_init_data){
3760 .hw.init = &(struct clk_init_data) {
3764 &g12a_cts_enci_sel.hw
3776 .hw.init = &(struct clk_init_data) {
3780 &g12a_cts_encp_sel.hw
3792 .hw.init = &(struct clk_init_data) {
3796 &g12a_cts_encl_sel.hw
3808 .hw.init = &(struct clk_init_data) {
3812 &g12a_cts_vdac_sel.hw
3824 .hw.init = &(struct clk_init_data) {
3828 &g12a_hdmi_tx_sel.hw
3838 &g12a_vid_pll.hw,
3839 &g12a_gp0_pll.hw,
3840 &g12a_hifi_pll.hw,
3841 &g12a_mpll1.hw,
3842 &g12a_fclk_div2.hw,
3843 &g12a_fclk_div2p5.hw,
3844 &g12a_fclk_div3.hw,
3845 &g12a_fclk_div7.hw,
3855 .hw.init = &(struct clk_init_data){
3881 .hw.init = &(struct clk_init_data){
3885 &g12a_mipi_dsi_pxclk_sel.hw
3897 .hw.init = &(struct clk_init_data) {
3901 &g12a_mipi_dsi_pxclk_div.hw
3912 { .hw = &g12a_gp0_pll.hw },
3913 { .hw = &g12a_hifi_pll.hw },
3914 { .hw = &g12a_fclk_div2p5.hw },
3915 { .hw = &g12a_fclk_div3.hw },
3916 { .hw = &g12a_fclk_div4.hw },
3917 { .hw = &g12a_fclk_div5.hw },
3918 { .hw = &g12a_fclk_div7.hw },
3927 .hw.init = &(struct clk_init_data){
3941 .hw.init = &(struct clk_init_data){
3945 &g12b_mipi_isp_sel.hw
3957 .hw.init = &(struct clk_init_data) {
3961 &g12b_mipi_isp_div.hw
3972 { .hw = &g12a_fclk_div4.hw },
3973 { .hw = &g12a_fclk_div3.hw },
3974 { .hw = &g12a_fclk_div5.hw },
3984 .hw.init = &(struct clk_init_data){
3999 .hw.init = &(struct clk_init_data){
4002 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_sel.hw },
4013 .hw.init = &(struct clk_init_data) {
4016 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_div.hw },
4030 { .hw = &g12a_gp0_pll.hw },
4031 { .hw = &g12a_hifi_pll.hw },
4032 { .hw = &g12a_fclk_div2p5.hw },
4033 { .hw = &g12a_fclk_div3.hw },
4034 { .hw = &g12a_fclk_div4.hw },
4035 { .hw = &g12a_fclk_div5.hw },
4036 { .hw = &g12a_fclk_div7.hw },
4045 .hw.init = &(struct clk_init_data){
4066 .hw.init = &(struct clk_init_data){
4070 &g12a_mali_0_sel.hw
4082 .hw.init = &(struct clk_init_data){
4086 &g12a_mali_0_div.hw
4099 .hw.init = &(struct clk_init_data){
4120 .hw.init = &(struct clk_init_data){
4124 &g12a_mali_1_sel.hw
4136 .hw.init = &(struct clk_init_data){
4140 &g12a_mali_1_div.hw
4148 &g12a_mali_0.hw,
4149 &g12a_mali_1.hw,
4158 .hw.init = &(struct clk_init_data){
4173 .hw.init = &(struct clk_init_data){
4188 .hw.init = &(struct clk_init_data){
4192 &g12a_ts_div.hw
4202 { .hw = &g12a_clk81.hw },
4203 { .hw = &g12a_fclk_div4.hw },
4204 { .hw = &g12a_fclk_div3.hw },
4205 { .hw = &g12a_fclk_div2.hw },
4206 { .hw = &g12a_fclk_div5.hw },
4207 { .hw = &g12a_fclk_div7.hw },
4216 .hw.init = &(struct clk_init_data){
4230 .hw.init = &(struct clk_init_data){
4234 &g12a_spicc0_sclk_sel.hw
4246 .hw.init = &(struct clk_init_data){
4250 &g12a_spicc0_sclk_div.hw
4263 .hw.init = &(struct clk_init_data){
4277 .hw.init = &(struct clk_init_data){
4281 &g12a_spicc1_sclk_sel.hw
4293 .hw.init = &(struct clk_init_data){
4297 &g12a_spicc1_sclk_div.hw
4308 { .hw = &g12a_gp0_pll.hw, },
4309 { .hw = &g12a_hifi_pll.hw, },
4310 { .hw = &g12a_fclk_div2p5.hw, },
4311 { .hw = &g12a_fclk_div3.hw, },
4312 { .hw = &g12a_fclk_div4.hw, },
4313 { .hw = &g12a_fclk_div5.hw, },
4314 { .hw = &g12a_fclk_div7.hw },
4323 .hw.init = &(struct clk_init_data){
4337 .hw.init = &(struct clk_init_data){
4341 &sm1_nna_axi_clk_sel.hw
4353 .hw.init = &(struct clk_init_data){
4357 &sm1_nna_axi_clk_div.hw
4370 .hw.init = &(struct clk_init_data){
4384 .hw.init = &(struct clk_init_data){
4388 &sm1_nna_core_clk_sel.hw
4400 .hw.init = &(struct clk_init_data){
4404 &sm1_nna_core_clk_div.hw
4412 MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
4415 MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw)
4497 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4498 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4499 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4500 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4501 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4502 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4503 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4504 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4505 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4506 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4507 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4508 [CLKID_CLK81] = &g12a_clk81.hw,
4509 [CLKID_MPLL0] = &g12a_mpll0.hw,
4510 [CLKID_MPLL1] = &g12a_mpll1.hw,
4511 [CLKID_MPLL2] = &g12a_mpll2.hw,
4512 [CLKID_MPLL3] = &g12a_mpll3.hw,
4513 [CLKID_DDR] = &g12a_ddr.hw,
4514 [CLKID_DOS] = &g12a_dos.hw,
4515 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4516 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4517 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4518 [CLKID_ISA] = &g12a_isa.hw,
4519 [CLKID_PL301] = &g12a_pl301.hw,
4520 [CLKID_PERIPHS] = &g12a_periphs.hw,
4521 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4522 [CLKID_I2C] = &g12a_i2c.hw,
4523 [CLKID_SANA] = &g12a_sana.hw,
4524 [CLKID_SD] = &g12a_sd.hw,
4525 [CLKID_RNG0] = &g12a_rng0.hw,
4526 [CLKID_UART0] = &g12a_uart0.hw,
4527 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4528 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4529 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4530 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4531 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4532 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4533 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4534 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4535 [CLKID_AUDIO] = &g12a_audio.hw,
4536 [CLKID_ETH] = &g12a_eth_core.hw,
4537 [CLKID_DEMUX] = &g12a_demux.hw,
4538 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4539 [CLKID_ADC] = &g12a_adc.hw,
4540 [CLKID_UART1] = &g12a_uart1.hw,
4541 [CLKID_G2D] = &g12a_g2d.hw,
4542 [CLKID_RESET] = &g12a_reset.hw,
4543 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4544 [CLKID_PARSER] = &g12a_parser.hw,
4545 [CLKID_USB] = &g12a_usb_general.hw,
4546 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4547 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4548 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4549 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4550 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4551 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4552 [CLKID_BT656] = &g12a_bt656.hw,
4553 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4554 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4555 [CLKID_UART2] = &g12a_uart2.hw,
4556 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4557 [CLKID_GIC] = &g12a_gic.hw,
4558 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4559 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4560 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4561 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4562 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4563 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4564 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4565 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4566 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4567 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4568 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4569 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4570 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4571 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4572 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4573 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4574 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4575 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4576 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4577 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4578 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4579 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4580 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4581 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4582 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4583 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4584 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4585 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4586 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4587 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4588 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4589 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4590 [CLKID_ENC480P] = &g12a_enc480p.hw,
4591 [CLKID_RNG1] = &g12a_rng1.hw,
4592 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4593 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4594 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4595 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4596 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4597 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4598 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4599 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4600 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4601 [CLKID_DMA] = &g12a_dma.hw,
4602 [CLKID_EFUSE] = &g12a_efuse.hw,
4603 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4604 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4605 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4606 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4607 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4608 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4609 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4610 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4611 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4612 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4613 [CLKID_VPU] = &g12a_vpu.hw,
4614 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4615 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4616 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4617 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4618 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4619 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4620 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4621 [CLKID_VAPB] = &g12a_vapb.hw,
4622 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4623 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4624 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4625 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4626 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4627 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4628 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4629 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4630 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4631 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4632 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4633 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4634 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4635 [CLKID_VCLK] = &g12a_vclk.hw,
4636 [CLKID_VCLK2] = &g12a_vclk2.hw,
4637 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4638 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4639 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4640 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4641 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4642 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4643 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4644 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4645 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4646 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4647 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4648 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4649 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4650 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4651 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4652 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4653 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4654 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4655 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4656 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4657 [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,
4658 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4659 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4660 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4661 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4662 [CLKID_CTS_ENCL] = &g12a_cts_encl.hw,
4663 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4664 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4665 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4666 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4667 [CLKID_HDMI] = &g12a_hdmi.hw,
4668 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4669 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4670 [CLKID_MALI_0] = &g12a_mali_0.hw,
4671 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4672 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4673 [CLKID_MALI_1] = &g12a_mali_1.hw,
4674 [CLKID_MALI] = &g12a_mali.hw,
4675 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4676 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4677 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4678 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4679 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4680 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4681 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4682 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4683 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4684 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4685 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4686 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
4687 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4688 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4689 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4690 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4691 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4692 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4693 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4694 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4695 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4696 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4697 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4698 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4699 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4700 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4701 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4702 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4703 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4704 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4705 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4706 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4707 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4708 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4709 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4710 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4711 [CLKID_TS] = &g12a_ts.hw,
4712 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
4713 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
4714 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
4715 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
4716 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
4717 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
4718 [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
4719 [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
4720 [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
4724 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4725 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4726 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4727 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4728 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4729 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4730 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4731 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4732 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4733 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4734 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4735 [CLKID_CLK81] = &g12a_clk81.hw,
4736 [CLKID_MPLL0] = &g12a_mpll0.hw,
4737 [CLKID_MPLL1] = &g12a_mpll1.hw,
4738 [CLKID_MPLL2] = &g12a_mpll2.hw,
4739 [CLKID_MPLL3] = &g12a_mpll3.hw,
4740 [CLKID_DDR] = &g12a_ddr.hw,
4741 [CLKID_DOS] = &g12a_dos.hw,
4742 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4743 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4744 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4745 [CLKID_ISA] = &g12a_isa.hw,
4746 [CLKID_PL301] = &g12a_pl301.hw,
4747 [CLKID_PERIPHS] = &g12a_periphs.hw,
4748 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4749 [CLKID_I2C] = &g12a_i2c.hw,
4750 [CLKID_SANA] = &g12a_sana.hw,
4751 [CLKID_SD] = &g12a_sd.hw,
4752 [CLKID_RNG0] = &g12a_rng0.hw,
4753 [CLKID_UART0] = &g12a_uart0.hw,
4754 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4755 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4756 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4757 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4758 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4759 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4760 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4761 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4762 [CLKID_AUDIO] = &g12a_audio.hw,
4763 [CLKID_ETH] = &g12a_eth_core.hw,
4764 [CLKID_DEMUX] = &g12a_demux.hw,
4765 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4766 [CLKID_ADC] = &g12a_adc.hw,
4767 [CLKID_UART1] = &g12a_uart1.hw,
4768 [CLKID_G2D] = &g12a_g2d.hw,
4769 [CLKID_RESET] = &g12a_reset.hw,
4770 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4771 [CLKID_PARSER] = &g12a_parser.hw,
4772 [CLKID_USB] = &g12a_usb_general.hw,
4773 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4774 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4775 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4776 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4777 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4778 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4779 [CLKID_BT656] = &g12a_bt656.hw,
4780 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4781 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4782 [CLKID_UART2] = &g12a_uart2.hw,
4783 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4784 [CLKID_GIC] = &g12a_gic.hw,
4785 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4786 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4787 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4788 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4789 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4790 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4791 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4792 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4793 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4794 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4795 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4796 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4797 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4798 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4799 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4800 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4801 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4802 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4803 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4804 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4805 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4806 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4807 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4808 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4809 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4810 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4811 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4812 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4813 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4814 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4815 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4816 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4817 [CLKID_ENC480P] = &g12a_enc480p.hw,
4818 [CLKID_RNG1] = &g12a_rng1.hw,
4819 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4820 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4821 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4822 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4823 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4824 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4825 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4826 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4827 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4828 [CLKID_DMA] = &g12a_dma.hw,
4829 [CLKID_EFUSE] = &g12a_efuse.hw,
4830 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4831 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4832 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4833 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4834 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4835 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4836 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4837 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4838 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4839 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4840 [CLKID_VPU] = &g12a_vpu.hw,
4841 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4842 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4843 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4844 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4845 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4846 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4847 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4848 [CLKID_VAPB] = &g12a_vapb.hw,
4849 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4850 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4851 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4852 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4853 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4854 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4855 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4856 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4857 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4858 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4859 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4860 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4861 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4862 [CLKID_VCLK] = &g12a_vclk.hw,
4863 [CLKID_VCLK2] = &g12a_vclk2.hw,
4864 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4865 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4866 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4867 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4868 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4869 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4870 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4871 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4872 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4873 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4874 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4875 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4876 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4877 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4878 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4879 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4880 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4881 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4882 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4883 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4884 [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,
4885 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4886 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4887 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4888 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4889 [CLKID_CTS_ENCL] = &g12a_cts_encl.hw,
4890 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4891 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4892 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4893 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4894 [CLKID_HDMI] = &g12a_hdmi.hw,
4895 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4896 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4897 [CLKID_MALI_0] = &g12a_mali_0.hw,
4898 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4899 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4900 [CLKID_MALI_1] = &g12a_mali_1.hw,
4901 [CLKID_MALI] = &g12a_mali.hw,
4902 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4903 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4904 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4905 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4906 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4907 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4908 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4909 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4910 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4911 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4912 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4913 [CLKID_CPU_CLK] = &g12b_cpu_clk.hw,
4914 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4915 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4916 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4917 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4918 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4919 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4920 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4921 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4922 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4923 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4924 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4925 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4926 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4927 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4928 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4929 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4930 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4931 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4932 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4933 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4934 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4935 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4936 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4937 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4938 [CLKID_TS] = &g12a_ts.hw,
4939 [CLKID_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw,
4940 [CLKID_SYS1_PLL] = &g12b_sys1_pll.hw,
4941 [CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw,
4942 [CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw,
4943 [CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_premux0.hw,
4944 [CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_mux0_div.hw,
4945 [CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_postmux0.hw,
4946 [CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_premux1.hw,
4947 [CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_mux1_div.hw,
4948 [CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_postmux1.hw,
4949 [CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw,
4950 [CLKID_CPUB_CLK] = &g12b_cpub_clk.hw,
4951 [CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw,
4952 [CLKID_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw,
4953 [CLKID_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw,
4954 [CLKID_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw,
4955 [CLKID_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw,
4956 [CLKID_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw,
4957 [CLKID_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw,
4958 [CLKID_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw,
4959 [CLKID_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw,
4960 [CLKID_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw,
4961 [CLKID_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw,
4962 [CLKID_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw,
4963 [CLKID_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw,
4964 [CLKID_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw,
4965 [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw,
4966 [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw,
4967 [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw,
4968 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
4969 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
4970 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
4971 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
4972 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
4973 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
4974 [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
4975 [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
4976 [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
4977 [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
4978 [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
4979 [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
4980 [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
4981 [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
4982 [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
4983 [CLKID_MIPI_ISP_SEL] = &g12b_mipi_isp_sel.hw,
4984 [CLKID_MIPI_ISP_DIV] = &g12b_mipi_isp_div.hw,
4985 [CLKID_MIPI_ISP] = &g12b_mipi_isp.hw,
4986 [CLKID_MIPI_ISP_GATE] = &g12b_mipi_isp_gate.hw,
4987 [CLKID_MIPI_ISP_CSI_PHY0] = &g12b_csi_phy0.hw,
4988 [CLKID_MIPI_ISP_CSI_PHY1] = &g12b_csi_phy1.hw,
4992 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4993 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4994 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4995 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4996 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4997 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4998 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4999 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
5000 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
5001 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
5002 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
5003 [CLKID_CLK81] = &g12a_clk81.hw,
5004 [CLKID_MPLL0] = &g12a_mpll0.hw,
5005 [CLKID_MPLL1] = &g12a_mpll1.hw,
5006 [CLKID_MPLL2] = &g12a_mpll2.hw,
5007 [CLKID_MPLL3] = &g12a_mpll3.hw,
5008 [CLKID_DDR] = &g12a_ddr.hw,
5009 [CLKID_DOS] = &g12a_dos.hw,
5010 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
5011 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
5012 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
5013 [CLKID_ISA] = &g12a_isa.hw,
5014 [CLKID_PL301] = &g12a_pl301.hw,
5015 [CLKID_PERIPHS] = &g12a_periphs.hw,
5016 [CLKID_SPICC0] = &g12a_spicc_0.hw,
5017 [CLKID_I2C] = &g12a_i2c.hw,
5018 [CLKID_SANA] = &g12a_sana.hw,
5019 [CLKID_SD] = &g12a_sd.hw,
5020 [CLKID_RNG0] = &g12a_rng0.hw,
5021 [CLKID_UART0] = &g12a_uart0.hw,
5022 [CLKID_SPICC1] = &g12a_spicc_1.hw,
5023 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
5024 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
5025 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
5026 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
5027 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
5028 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
5029 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
5030 [CLKID_AUDIO] = &g12a_audio.hw,
5031 [CLKID_ETH] = &g12a_eth_core.hw,
5032 [CLKID_DEMUX] = &g12a_demux.hw,
5033 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
5034 [CLKID_ADC] = &g12a_adc.hw,
5035 [CLKID_UART1] = &g12a_uart1.hw,
5036 [CLKID_G2D] = &g12a_g2d.hw,
5037 [CLKID_RESET] = &g12a_reset.hw,
5038 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
5039 [CLKID_PARSER] = &g12a_parser.hw,
5040 [CLKID_USB] = &g12a_usb_general.hw,
5041 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
5042 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
5043 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
5044 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
5045 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
5046 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
5047 [CLKID_BT656] = &g12a_bt656.hw,
5048 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
5049 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
5050 [CLKID_UART2] = &g12a_uart2.hw,
5051 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
5052 [CLKID_GIC] = &g12a_gic.hw,
5053 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
5054 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
5055 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
5056 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
5057 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
5058 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
5059 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
5060 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
5061 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
5062 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
5063 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
5064 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
5065 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
5066 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
5067 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
5068 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
5069 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
5070 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
5071 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
5072 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
5073 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
5074 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
5075 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
5076 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
5077 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
5078 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
5079 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
5080 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
5081 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
5082 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
5083 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
5084 [CLKID_IEC958] = &g12a_iec958_gate.hw,
5085 [CLKID_ENC480P] = &g12a_enc480p.hw,
5086 [CLKID_RNG1] = &g12a_rng1.hw,
5087 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
5088 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
5089 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
5090 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
5091 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
5092 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
5093 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
5094 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
5095 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
5096 [CLKID_DMA] = &g12a_dma.hw,
5097 [CLKID_EFUSE] = &g12a_efuse.hw,
5098 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
5099 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
5100 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
5101 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
5102 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
5103 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
5104 [CLKID_VPU_0] = &g12a_vpu_0.hw,
5105 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
5106 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
5107 [CLKID_VPU_1] = &g12a_vpu_1.hw,
5108 [CLKID_VPU] = &g12a_vpu.hw,
5109 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
5110 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
5111 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
5112 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
5113 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
5114 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
5115 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
5116 [CLKID_VAPB] = &g12a_vapb.hw,
5117 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
5118 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
5119 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
5120 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
5121 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
5122 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
5123 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
5124 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
5125 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
5126 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
5127 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
5128 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
5129 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
5130 [CLKID_VCLK] = &g12a_vclk.hw,
5131 [CLKID_VCLK2] = &g12a_vclk2.hw,
5132 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
5133 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
5134 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
5135 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
5136 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
5137 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
5138 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
5139 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
5140 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
5141 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
5142 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
5143 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
5144 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
5145 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
5146 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
5147 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
5148 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
5149 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
5150 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
5151 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
5152 [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,
5153 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
5154 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
5155 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
5156 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
5157 [CLKID_CTS_ENCL] = &g12a_cts_encl.hw,
5158 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
5159 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
5160 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
5161 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
5162 [CLKID_HDMI] = &g12a_hdmi.hw,
5163 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
5164 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
5165 [CLKID_MALI_0] = &g12a_mali_0.hw,
5166 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
5167 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
5168 [CLKID_MALI_1] = &g12a_mali_1.hw,
5169 [CLKID_MALI] = &g12a_mali.hw,
5170 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
5171 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
5172 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
5173 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
5174 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
5175 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
5176 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
5177 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
5178 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
5179 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
5180 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
5181 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
5182 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
5183 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
5184 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
5185 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
5186 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
5187 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
5188 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
5189 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
5190 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
5191 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
5192 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
5193 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
5194 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
5195 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
5196 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
5197 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
5198 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
5199 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
5200 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
5201 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
5202 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
5203 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
5204 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
5205 [CLKID_TS_DIV] = &g12a_ts_div.hw,
5206 [CLKID_TS] = &g12a_ts.hw,
5207 [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
5208 [CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
5209 [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw,
5210 [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw,
5211 [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw,
5212 [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw,
5213 [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw,
5214 [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw,
5215 [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
5216 [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
5217 [CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
5218 [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
5219 [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
5220 [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
5221 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
5222 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
5223 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
5224 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
5225 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
5226 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
5227 [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
5228 [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
5229 [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
5230 [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
5231 [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
5232 [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
5233 [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
5234 [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
5235 [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
5255 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_postmux0.hw,
5265 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_dyn.hw,
5292 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpu_clk.hw,
5302 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_sys1_pll.hw,
5315 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_postmux0.hw,
5325 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_dyn.hw, "dvfs");
5334 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk.hw, DVFS_CON_ID);
5343 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID);
5366 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk.hw, DVFS_CON_ID);
5375 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID);