clk/mediatek/clk-mux.c

18 #include "clk-mux.h"
35 	struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
38 	if (mux->lock)
39 		spin_lock_irqsave(mux->lock, flags);
41 		__acquire(mux->lock);
43 	regmap_write(mux->regmap, mux->data->clr_ofs,
44 		     BIT(mux->data->gate_shift));
48 	 * not be effective yet. Set the update bit to ensure the mux gets
51 	if (mux->reparent && mux->data->upd_shift >= 0) {
52 		regmap_write(mux->regmap, mux->data->upd_ofs,
53 			     BIT(mux->data->upd_shift));
54 		mux->reparent = false;
57 	if (mux->lock)
58 		spin_unlock_irqrestore(mux->lock, flags);
60 		__release(mux->lock);
67 	struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
69 	regmap_write(mux->regmap, mux->data->set_ofs,
70 			BIT(mux->data->gate_shift));
75 	struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
78 	regmap_read(mux->regmap, mux->data->mux_ofs, &val);
80 	return (val & BIT(mux->data->gate_shift)) == 0;
85 	struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
86 	u32 mask = GENMASK(mux->data->mux_width - 1, 0);
89 	regmap_read(mux->regmap, mux->data->mux_ofs, &val);
90 	val = (val >> mux->data->mux_shift) & mask;
92 	if (mux->data->parent_index) {
95 		for (i = 0; i < mux->data->num_parents; i++)
96 			if (mux->data->parent_index[i] == val)
100 		return mux->data->num_parents + 1;
108 	struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
109 	u32 mask = GENMASK(mux->data->mux_width - 1, 0);
113 	if (mux->lock)
114 		spin_lock_irqsave(mux->lock, flags);
116 		__acquire(mux->lock);
118 	if (mux->data->parent_index)
119 		index = mux->data->parent_index[index];
121 	regmap_read(mux->regmap, mux->data->mux_ofs, &orig);
122 	val = (orig & ~(mask << mux->data->mux_shift))
123 			| (index << mux->data->mux_shift);
126 		regmap_write(mux->regmap, mux->data->clr_ofs,
127 				mask << mux->data->mux_shift);
128 		regmap_write(mux->regmap, mux->data->set_ofs,
129 				index << mux->data->mux_shift);
131 		if (mux->data->upd_shift >= 0) {
132 			regmap_write(mux->regmap, mux->data->upd_ofs,
133 					BIT(mux->data->upd_shift));
134 			mux->reparent = true;
138 	if (mux->lock)
139 		spin_unlock_irqrestore(mux->lock, flags);
141 		__release(mux->lock);
149 	struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
151 	return clk_mux_determine_rate_flags(hw, req, mux->data->flags);
172 					   const struct mtk_mux *mux,
184 	init.name = mux->name;
185 	init.flags = mux->flags;
186 	init.parent_names = mux->parent_names;
187 	init.num_parents = mux->num_parents;
188 	init.ops = mux->ops;
191 	clk_mux->data = mux;
206 	struct mtk_clk_mux *mux;
210 	mux = to_mtk_clk_mux(hw);
213 	kfree(mux);
233 		const struct mtk_mux *mux = &muxes[i];
235 		if (!IS_ERR_OR_NULL(clk_data->hws[mux->id])) {
237 				node, mux->id);
241 		hw = mtk_clk_register_mux(dev, mux, regmap, lock);
244 			pr_err("Failed to register clk %s: %pe\n", mux->name,
249 		clk_data->hws[mux->id] = hw;
256 		const struct mtk_mux *mux = &muxes[i];
258 		if (IS_ERR_OR_NULL(clk_data->hws[mux->id]))
261 		mtk_clk_unregister_mux(clk_data->hws[mux->id]);
262 		clk_data->hws[mux->id] = ERR_PTR(-ENOENT);
278 		const struct mtk_mux *mux = &muxes[i - 1];
280 		if (IS_ERR_OR_NULL(clk_data->hws[mux->id]))
283 		mtk_clk_unregister_mux(clk_data->hws[mux->id]);
284 		clk_data->hws[mux->id] = ERR_PTR(-ENOENT);