drivers/clk/clk-xgene.c

446 	struct xgene_clk *pclk = to_xgene_clk(hw);
450 	if (pclk->lock)
451 		spin_lock_irqsave(pclk->lock, flags);
453 	if (pclk->param.csr_reg) {
456 		data = xgene_clk_read(pclk->param.csr_reg +
457 					pclk->param.reg_clk_offset);
458 		data |= pclk->param.reg_clk_mask;
459 		xgene_clk_write(data, pclk->param.csr_reg +
460 					pclk->param.reg_clk_offset);
463 			pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,
467 		data = xgene_clk_read(pclk->param.csr_reg +
468 					pclk->param.reg_csr_offset);
469 		data &= ~pclk->param.reg_csr_mask;
470 		xgene_clk_write(data, pclk->param.csr_reg +
471 					pclk->param.reg_csr_offset);
474 			pclk->param.reg_csr_offset, pclk->param.reg_csr_mask,
478 	if (pclk->lock)
479 		spin_unlock_irqrestore(pclk->lock, flags);
486 	struct xgene_clk *pclk = to_xgene_clk(hw);
490 	if (pclk->lock)
491 		spin_lock_irqsave(pclk->lock, flags);
493 	if (pclk->param.csr_reg) {
496 		data = xgene_clk_read(pclk->param.csr_reg +
497 					pclk->param.reg_csr_offset);
498 		data |= pclk->param.reg_csr_mask;
499 		xgene_clk_write(data, pclk->param.csr_reg +
500 					pclk->param.reg_csr_offset);
503 		data = xgene_clk_read(pclk->param.csr_reg +
504 					pclk->param.reg_clk_offset);
505 		data &= ~pclk->param.reg_clk_mask;
506 		xgene_clk_write(data, pclk->param.csr_reg +
507 					pclk->param.reg_clk_offset);
510 	if (pclk->lock)
511 		spin_unlock_irqrestore(pclk->lock, flags);
516 	struct xgene_clk *pclk = to_xgene_clk(hw);
519 	if (pclk->param.csr_reg) {
521 		data = xgene_clk_read(pclk->param.csr_reg +
522 					pclk->param.reg_clk_offset);
524 			str_enabled_disabled(data & pclk->param.reg_clk_mask));
529 	return data & pclk->param.reg_clk_mask ? 1 : 0;
535 	struct xgene_clk *pclk = to_xgene_clk(hw);
538 	if (pclk->param.divider_reg) {
539 		data = xgene_clk_read(pclk->param.divider_reg +
540 					pclk->param.reg_divider_offset);
541 		data >>= pclk->param.reg_divider_shift;
542 		data &= (1 << pclk->param.reg_divider_width) - 1;
559 	struct xgene_clk *pclk = to_xgene_clk(hw);
565 	if (pclk->lock)
566 		spin_lock_irqsave(pclk->lock, flags);
568 	if (pclk->param.divider_reg) {
573 		divider &= (1 << pclk->param.reg_divider_width) - 1;
574 		divider <<= pclk->param.reg_divider_shift;
577 		data = xgene_clk_read(pclk->param.divider_reg +
578 				pclk->param.reg_divider_offset);
579 		data &= ~(((1 << pclk->param.reg_divider_width) - 1)
580 				<< pclk->param.reg_divider_shift);
582 		xgene_clk_write(data, pclk->param.divider_reg +
583 					pclk->param.reg_divider_offset);
590 	if (pclk->lock)
591 		spin_unlock_irqrestore(pclk->lock, flags);
599 	struct xgene_clk *pclk = to_xgene_clk(hw);
603 	if (pclk->param.divider_reg) {