drivers/clk/clk-vt8500.c

124 	/* div == 0 is actually the highest divisor */
135 	u32 divisor;
140 	divisor = *prate / rate;
142 	/* If prate / rate would be decimal, incr the divisor */
143 	if (rate * divisor < *prate)
144 		divisor++;
147 	 * If this is a request for SDMMC we have to adjust the divisor
150 	if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
151 		divisor = 64 * ((divisor / 64) + 1);
154 	return *prate / divisor;
161 	u32 divisor;
167 	divisor =  parent_rate / rate;
169 	if (divisor == cdev->div_mask + 1)
170 		divisor = 0;
173 	if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
175 		 * Bit 5 is a fixed /64 predivisor. If the requested divisor
176 		 * is >31 then correct for the fixed divisor being required.
178 		divisor = 0x20 + (divisor / 64);
181 	if (divisor > cdev->div_mask) {
182 		pr_err("%s: invalid divisor for clock\n", __func__);
189 	writel(divisor, cdev->div_reg);
255 	rc = of_property_read_u32(node, "divisor-reg", &div_reg);
264 		of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask);
427 	/* calculate frequency (MHz) after pre-divisor */