drivers/clk/clk-versaclock3.c

143 	u8 mdiv1_bitmsk;
257 		if (prediv & pfd->mdiv1_bitmsk) {
267 		if (prediv & pfd->mdiv1_bitmsk) {
278 		if (prediv & pfd->mdiv1_bitmsk)
329 		regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv1_bitmsk,
330 				   pfd->mdiv1_bitmsk);
340 		regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv1_bitmsk, 0);
634 			.mdiv1_bitmsk = VC3_PLL1_M_DIV1,
651 			.mdiv1_bitmsk = VC3_PLL2_M_DIV1,
668 			.mdiv1_bitmsk = VC3_PLL3_M_DIV1,