Lines Matching refs:clk_reg
36 u32 clk_reg;
58 .clk_reg = MAX77686_REG_32KHZ,
63 .clk_reg = MAX77686_REG_32KHZ,
68 .clk_reg = MAX77686_REG_32KHZ,
77 .clk_reg = MAX77802_REG_32KHZ,
82 .clk_reg = MAX77802_REG_32KHZ,
91 .clk_reg = MAX77620_REG_CNFG1_32K,
106 return regmap_update_bits(max77686->regmap, max77686->clk_info->clk_reg,
115 regmap_update_bits(max77686->regmap, max77686->clk_info->clk_reg,
126 ret = regmap_read(max77686->regmap, max77686->clk_info->clk_reg, &val);