clk/axs10x/pll_clock.c

94 	const struct axs10x_pll_cfg *pll_cfg;
158 	const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg;
160 	if (pll_cfg[0].rate == 0)
163 	best_rate = pll_cfg[0].rate;
165 	for (i = 1; pll_cfg[i].rate != 0; i++) {
166 		if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
167 			best_rate = pll_cfg[i].rate;
178 	const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg;
180 	for (i = 0; pll_cfg[i].rate != 0; i++) {
181 		if (pll_cfg[i].rate == rate) {
183 					 axs10x_encode_div(pll_cfg[i].idiv, 0));
185 					 axs10x_encode_div(pll_cfg[i].fbdiv, 0));
187 					 axs10x_encode_div(pll_cfg[i].odiv, 1));
242 	pll_clk->pll_cfg = of_device_get_match_data(dev);
244 	if (!pll_clk->pll_cfg) {
288 	pll_clk->pll_cfg = arc_pll_cfg;