drivers/ata/sata_nv.c

600 	struct nv_adma_port_priv *pp = ap->private_data;
601 	void __iomem *mmio = pp->ctl_block;
605 	if (pp->flags & NV_ADMA_PORT_REGISTER_MODE)
633 	pp->flags |= NV_ADMA_PORT_REGISTER_MODE;
638 	struct nv_adma_port_priv *pp = ap->private_data;
639 	void __iomem *mmio = pp->ctl_block;
643 	if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE))
646 	WARN_ON(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);
663 	pp->flags &= ~NV_ADMA_PORT_REGISTER_MODE;
670 	struct nv_adma_port_priv *pp = ap->private_data;
721 		pp->flags &= ~NV_ADMA_ATAPI_SETUP_COMPLETE;
724 		pp->flags |= NV_ADMA_ATAPI_SETUP_COMPLETE;
743 		rc = dma_set_mask(&pdev->dev, pp->adma_dma_mask);
760 	struct nv_adma_port_priv *pp = qc->ap->private_data;
761 	return !(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);
812 	struct nv_adma_port_priv *pp = ap->private_data;
813 	u8 flags = pp->cpb[cpb_num].resp_flags;
889 		struct nv_adma_port_priv *pp = ap->private_data;
890 		void __iomem *mmio = pp->ctl_block;
898 		if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) {
906 		if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) {
922 		gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);
1004 		struct nv_adma_port_priv *pp = host->ports[0]->private_data;
1005 		writel(notifier_clears[0], pp->notifier_clear_block);
1006 		pp = host->ports[1]->private_data;
1007 		writel(notifier_clears[1], pp->notifier_clear_block);
1017 	struct nv_adma_port_priv *pp = ap->private_data;
1018 	void __iomem *mmio = pp->ctl_block;
1023 	if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
1039 	struct nv_adma_port_priv *pp = ap->private_data;
1040 	void __iomem *mmio = pp->ctl_block;
1045 	if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
1057 	struct nv_adma_port_priv *pp = ap->private_data;
1058 	void __iomem *mmio = pp->ctl_block;
1061 	if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) {
1082 	pp = ap->host->ports[0]->private_data;
1083 	writel(notifier_clears[0], pp->notifier_clear_block);
1084 	pp = ap->host->ports[1]->private_data;
1085 	writel(notifier_clears[1], pp->notifier_clear_block);
1090 	struct nv_adma_port_priv *pp = qc->ap->private_data;
1092 	if (pp->flags & NV_ADMA_PORT_REGISTER_MODE)
1099 	struct nv_adma_port_priv *pp;
1120 	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1121 	if (!pp)
1126 	pp->ctl_block = mmio;
1127 	pp->gen_block = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_GEN;
1128 	pp->notifier_clear_block = pp->gen_block +
1137 	pp->adma_dma_mask = *dev->dma_mask;
1149 	pp->cpb     = mem;
1150 	pp->cpb_dma = mem_dma;
1161 	pp->aprd = mem;
1162 	pp->aprd_dma = mem_dma;
1164 	ap->private_data = pp;
1170 	pp->flags = NV_ADMA_PORT_REGISTER_MODE;
1192 	struct nv_adma_port_priv *pp = ap->private_data;
1193 	void __iomem *mmio = pp->ctl_block;
1201 	struct nv_adma_port_priv *pp = ap->private_data;
1202 	void __iomem *mmio = pp->ctl_block;
1218 	struct nv_adma_port_priv *pp = ap->private_data;
1219 	void __iomem *mmio = pp->ctl_block;
1223 	writel(pp->cpb_dma & 0xFFFFFFFF, 	mmio + NV_ADMA_CPB_BASE_LOW);
1224 	writel((pp->cpb_dma >> 16) >> 16,	mmio + NV_ADMA_CPB_BASE_HIGH);
1230 	pp->flags |= NV_ADMA_PORT_REGISTER_MODE;
1315 	struct nv_adma_port_priv *pp = qc->ap->private_data;
1322 			&pp->aprd[NV_ADMA_SGTBL_LEN * qc->hw_tag + (si-5)];
1326 		cpb->next_aprd = cpu_to_le64(((u64)(pp->aprd_dma + NV_ADMA_SGTBL_SZ * qc->hw_tag)));
1333 	struct nv_adma_port_priv *pp = qc->ap->private_data;
1337 	if ((pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) ||
1350 	struct nv_adma_port_priv *pp = qc->ap->private_data;
1351 	struct nv_adma_cpb *cpb = &pp->cpb[qc->hw_tag];
1356 		BUG_ON(!(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) &&
1396 	struct nv_adma_port_priv *pp = qc->ap->private_data;
1397 	void __iomem *mmio = pp->ctl_block;
1411 		BUG_ON(!(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) &&
1422 	if (curr_ncq != pp->last_issue_ncq) {
1426 		pp->last_issue_ncq = curr_ncq;
1630 	struct nv_adma_port_priv *pp = ap->private_data;
1631 	if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) {
1632 		void __iomem *mmio = pp->ctl_block;
1639 			u32 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);
1652 				struct nv_adma_cpb *cpb = &pp->cpb[i];
1667 			pp->cpb[i].ctl_flags &= ~NV_CPB_CTL_CPB_VALID;
1686 	struct nv_swncq_port_priv *pp = ap->private_data;
1687 	struct defer_queue *dq = &pp->defer_queue;
1697 	struct nv_swncq_port_priv *pp = ap->private_data;
1698 	struct defer_queue *dq = &pp->defer_queue;
1714 	struct nv_swncq_port_priv *pp = ap->private_data;
1716 	pp->dhfis_bits = 0;
1717 	pp->dmafis_bits = 0;
1718 	pp->sdbfis_bits = 0;
1719 	pp->ncq_flags = 0;
1724 	struct nv_swncq_port_priv *pp = ap->private_data;
1725 	struct defer_queue *dq = &pp->defer_queue;
1730 	pp->qc_active = 0;
1731 	pp->last_issue_tag = ATA_TAG_POISON;
1737 	struct nv_swncq_port_priv *pp = ap->private_data;
1739 	writew(fis, pp->irq_block);
1752 	struct nv_swncq_port_priv *pp = ap->private_data;
1762 		pp->qc_active, pp->defer_queue.defer_bits, pp->last_issue_tag,
1763 		pp->dhfis_bits, pp->dmafis_bits, pp->sdbfis_bits);
1769 	sactive = readl(pp->sactive_block);
1770 	done_mask = pp->qc_active ^ sactive;
1775 		if (pp->qc_active & (1 << i))
1784 			     (pp->dhfis_bits >> i) & 0x1,
1785 			     (pp->dmafis_bits >> i) & 0x1,
1786 			     (pp->sdbfis_bits >> i) & 0x1,
1925 	struct nv_swncq_port_priv *pp;
1933 	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1934 	if (!pp)
1937 	pp->prd = dmam_alloc_coherent(dev, ATA_PRD_TBL_SZ * ATA_MAX_QUEUE,
1938 				      &pp->prd_dma, GFP_KERNEL);
1939 	if (!pp->prd)
1942 	ap->private_data = pp;
1943 	pp->sactive_block = ap->ioaddr.scr_addr + 4 * SCR_ACTIVE;
1944 	pp->irq_block = mmio + NV_INT_STATUS_MCP55 + ap->port_no * 2;
1945 	pp->tag_block = mmio + NV_NCQ_REG_MCP55 + ap->port_no * 2;
1969 	struct nv_swncq_port_priv *pp = ap->private_data;
1973 	prd = pp->prd + ATA_MAX_PRD * qc->hw_tag;
2004 	struct nv_swncq_port_priv *pp = ap->private_data;
2009 	writel((1 << qc->hw_tag), pp->sactive_block);
2010 	pp->last_issue_tag = qc->hw_tag;
2011 	pp->dhfis_bits &= ~(1 << qc->hw_tag);
2012 	pp->dmafis_bits &= ~(1 << qc->hw_tag);
2013 	pp->qc_active |= (0x1 << qc->hw_tag);
2026 	struct nv_swncq_port_priv *pp = ap->private_data;
2031 	if (!pp->qc_active)
2067 	struct nv_swncq_port_priv *pp = ap->private_data;
2088 	sactive = readl(pp->sactive_block);
2089 	done_mask = pp->qc_active ^ sactive;
2091 	pp->qc_active &= ~done_mask;
2092 	pp->dhfis_bits &= ~done_mask;
2093 	pp->dmafis_bits &= ~done_mask;
2094 	pp->sdbfis_bits |= done_mask;
2103 	if (pp->qc_active & pp->dhfis_bits)
2106 	if ((pp->ncq_flags & ncq_saw_backout) ||
2107 	    (pp->qc_active ^ pp->dhfis_bits))
2116 		     ap->qc_active, pp->qc_active,
2117 		     pp->defer_queue.defer_bits, pp->dhfis_bits,
2118 		     pp->dmafis_bits, pp->last_issue_tag);
2123 		qc = ata_qc_from_tag(ap, pp->last_issue_tag);
2128 	if (pp->defer_queue.defer_bits) {
2140 	struct nv_swncq_port_priv *pp = ap->private_data;
2143 	tag = readb(pp->tag_block) >> 2;
2153 	struct nv_swncq_port_priv *pp = ap->private_data;
2167 	iowrite32(pp->prd_dma + ATA_PRD_TBL_SZ * qc->hw_tag,
2181 	struct nv_swncq_port_priv *pp = ap->private_data;
2200 	if (!pp->qc_active)
2221 		pp->ncq_flags |= ncq_saw_backout;
2225 		pp->ncq_flags |= ncq_saw_sdb;
2228 			pp->qc_active, pp->dhfis_bits,
2229 			pp->dmafis_bits, readl(pp->sactive_block));
2238 		pp->dhfis_bits |= (0x1 << pp->last_issue_tag);
2239 		pp->ncq_flags |= ncq_saw_d2h;
2240 		if (pp->ncq_flags & (ncq_saw_sdb | ncq_saw_backout)) {
2248 		    !(pp->ncq_flags & ncq_saw_dmas)) {
2253 			if (pp->defer_queue.defer_bits) {
2265 		pp->dmafis_bits |= (0x1 << nv_swncq_tag(ap));
2266 		pp->ncq_flags |= ncq_saw_dmas;
2412 			struct nv_adma_port_priv *pp;
2416 			pp = host->ports[0]->private_data;
2417 			if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
2423 			pp = host->ports[1]->private_data;
2424 			if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)