Lines Matching +full:broken +full:- +full:pio
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ata_piix.c - Intel PATA/SATA controllers
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
14 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
15 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
19 * as Documentation/driver-api/libata.rst
40 * PIIX4 errata #9 - Only on ultra obscure hw
41 * ICH3 errata #13 - Not observed to affect real hw
45 * PIIX4 errata #10 - BM IDE hang with non UDMA
47 * 440MX errata #15 - As PIIX4 errata #10
48 * PIIX4 errata #15 - Must not read control registers
49 * during a PIO transfer
50 * 440MX errata #13 - As PIIX4 errata #15
51 * ICH2 errata #21 - DMA mode 0 doesn't work right
52 * ICH0/1 errata #55 - As ICH2 errata #21
53 * ICH2 spec c #9 - Extra operations needed to handle
55 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
57 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
58 * ICH7 errata #16 - MWDMA1 timings are incorrect
61 * 450NX: errata #19 - DMA hangs on old 450NX
62 * 450NX: errata #20 - DMA hangs on old 450NX
63 * 450NX: errata #25 - Corruption with DMA on old 450NX
64 * ICH3 errata #15 - IDE deadlock under high load
66 * ICH3 errata #18 - Don't use native mode
100 PIIX_FLAG_PIO16 = (1 << 30), /*support 16bit PIO only*/
110 IDE = -1, /* IDE */
111 NA = -2, /* not available */
112 RV = -3, /* reserved */
116 /* host->flags bits */
181 /* Intel ICH4-L */
188 /* C-ICH (i810E2) */
194 /* ICH7/7-R (i945, i975) UDMA 100*/
206 /* 6300ESB (ICH5 variant with broken PCS present bits) */
296 /* SATA Controller IDE (Lynx Point-LP) */
298 /* SATA Controller IDE (Lynx Point-LP) */
300 /* SATA Controller IDE (Lynx Point-LP) */
302 /* SATA Controller IDE (Lynx Point-LP) */
451 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
475 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
479 { 0x24CA, 0x10CF, 0x11AB }, /* ICH4M on Fujitsu-Siemens Lifebook S6120 */
482 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
489 if (!(ap->flags & PIIX_FLAG_PIO16))
490 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
496 * ich_pata_cable_detect - Probe host controller cable detect info
508 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
509 struct piix_host_priv *hpriv = ap->host->private_data;
514 while (lap->device) {
515 if (lap->device == pdev->device &&
516 lap->subvendor == pdev->subsystem_vendor &&
517 lap->subdevice == pdev->subsystem_device)
524 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
525 if ((hpriv->saved_iocfg & mask) == 0)
531 * piix_pata_prereset - prereset for PATA host controller
540 struct ata_port *ap = link->ap;
541 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
543 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
544 return -ENOENT;
551 u8 pio)
553 struct pci_dev *dev = to_pci_dev(ap->host->dev);
555 unsigned int is_slave = (adev->devno != 0);
556 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
564 * See Intel Document 298600-004 for the timing programing rules
575 if (pio >= 2)
580 if (adev->class == ATA_DEV_ATA)
583 * If the drive MWDMA is faster than it can do PIO then
584 * we must force PIO into PIO0
586 if (adev->pio_mode < XFER_PIO_0 + pio)
588 control |= 8; /* PIO cycles in PIO0 */
592 /* PIO configuration clears DTE unconditionally. It will be
603 slave_data &= (ap->port_no ? 0x0f : 0xf0);
605 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
606 << (ap->port_no ? 4 : 0);
614 (timings[pio][0] << 12) |
615 (timings[pio][1] << 8);
624 /* Ensure the UDMA bit is off - it will be turned back on if
627 if (ap->udma_mask) {
629 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
637 * piix_set_piomode - Initialize host controller PATA PIO timings
641 * Set PIO mode for device, in host controller PCI config space.
649 piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0);
653 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
666 struct pci_dev *dev = to_pci_dev(ap->host->dev);
668 u8 speed = adev->dma_mode;
669 int devid = adev->devno + 2 * ap->port_no;
673 unsigned int udma = speed - XFER_UDMA_0;
689 u_speed = min(2 - (udma & 1), udma);
719 /* MWDMA is driven by the PIO timings. */
720 unsigned int mwdma = speed - XFER_MW_DMA_0;
724 int pio = needed_pio[mwdma] - XFER_PIO_0;
727 piix_set_timings(ap, adev, pio);
732 * piix_set_dmamode - Initialize host controller PATA DMA timings
748 * ich_set_dmamode - Initialize host controller PATA DMA timings
779 struct ata_port *ap = link->ap;
780 struct piix_host_priv *hpriv = ap->host->private_data;
782 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
783 hpriv->sidpr + PIIX_SIDPR_IDX);
789 struct piix_host_priv *hpriv = link->ap->host->private_data;
792 return -EINVAL;
795 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
802 struct piix_host_priv *hpriv = link->ap->host->private_data;
805 return -EINVAL;
808 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
822 if (unlikely(!ap->ioaddr.bmdma_addr))
825 host_stat = ap->ops->bmdma_status(ap);
961 .ident = "VGN-BX297XP",
964 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
1011 if (pdev->current_state == PCI_D0)
1012 pdev->current_state = PCI_UNKNOWN;
1014 /* tell resume that it's waking up from broken suspend */
1015 spin_lock_irqsave(&host->lock, flags);
1016 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1017 spin_unlock_irqrestore(&host->lock, flags);
1030 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1031 spin_lock_irqsave(&host->lock, flags);
1032 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1033 spin_unlock_irqrestore(&host->lock, flags);
1044 dev_err(&pdev->dev,
1117 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1125 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1130 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
1143 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
1233 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1239 * some Sandybridge chipsets have broken 32 mode up to now,
1291 return -ENOMEM;
1300 rc = -EIO;
1308 * piix_check_450nx_errata - Check for problem 450NX setup
1326 if (pdev->revision == 0x00)
1329 else if (cfg & (1<<14) && pdev->revision < 5)
1333 dev_warn(&ata_dev->dev,
1335 no_piix_dma == 2 ? " - a BIOS update may resolve this"
1344 struct pci_dev *pdev = to_pci_dev(host->dev);
1349 new_pcs = pcs | map_db->port_enable;
1369 map = map_db->map[map_value & map_db->mask];
1375 p += scnprintf(p, end - p, " XX");
1379 p += scnprintf(p, end - p, " --");
1386 p += scnprintf(p, end - p, " IDE IDE");
1390 p += scnprintf(p, end - p, " P%d", map[i]);
1396 dev_info(&pdev->dev, "MAP [%s ]\n", buf);
1399 dev_err(&pdev->dev, "invalid MAP value %u\n", map_value);
1406 struct pci_dev *pdev = to_pci_dev(host->dev);
1409 * Samsung DB-P70 only has three ATA ports exposed and
1426 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1427 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1428 pdev->subsystem_device == 0xb049) {
1429 dev_warn(host->dev,
1430 "Samsung DB-P70 detected, disabling SIDPR\n");
1439 struct pci_dev *pdev = to_pci_dev(host->dev);
1440 struct piix_host_priv *hpriv = host->private_data;
1441 struct ata_link *link0 = &host->ports[0]->link;
1447 if (hpriv->map[i] == IDE)
1453 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1463 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1472 * un-inhibit power save modes as BIOS might have inhibited
1481 dev_info(host->dev,
1489 struct ata_port *ap = host->ports[i];
1491 ap->ops = &piix_sidpr_sata_ops;
1493 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1520 struct pci_dev *pdev = to_pci_dev(host->dev);
1521 struct piix_host_priv *hpriv = host->private_data;
1530 if (hpriv->saved_iocfg & (1 << 18)) {
1531 dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n");
1533 hpriv->saved_iocfg & ~(1 << 18));
1543 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1552 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1564 unsigned long slot = (unsigned long)dmi->driver_data;
1565 /* apply the quirk only to on-board controllers */
1566 return slot == PCI_SLOT(pdev->devfn);
1575 "Prefer Hyper-V paravirtualization drivers instead of ATA, "
1576 "0 - Use ATA drivers, "
1577 "1 (Default) - Use the paravirtualization drivers.");
1584 /* On Hyper-V hypervisors the disks are exposed on
1590 .ident = "Hyper-V Virtual Machine",
1602 * identical to a Hyper-V guest. One difference is the
1621 host->flags |= ATA_HOST_IGNORE_ATA;
1622 dev_info(host->dev, "%s detected, ATA device ignore set\n",
1623 ignore->ident);
1629 * piix_init_one - Register PIIX ATA PCI device with kernel services
1640 * Zero on success, or -ERRNO value.
1645 struct device *dev = &pdev->dev;
1654 ata_print_version_once(&pdev->dev, DRV_VERSION);
1657 if (!in_module_init && ent->driver_data >= ich5_sata)
1658 return -ENODEV;
1661 piix_port_info[ent->driver_data].flags |=
1664 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1668 port_info[0] = piix_port_info[ent->driver_data];
1669 port_info[1] = piix_port_info[ent->driver_data];
1680 return -ENOMEM;
1687 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1693 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1701 hpriv->map = piix_init_sata_map(pdev, port_info,
1702 piix_map_db_table[ent->driver_data]);
1707 host->private_data = hpriv;
1711 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1715 if (host->ports[0]->ops == &piix_sidpr_sata_ops)
1726 * message-signalled interrupts currently).
1735 host->ports[0]->mwdma_mask = 0;
1736 host->ports[0]->udma_mask = 0;
1737 host->ports[1]->mwdma_mask = 0;
1738 host->ports[1]->udma_mask = 0;
1740 host->flags |= ATA_HOST_PARALLEL_SCAN;
1752 struct piix_host_priv *hpriv = host->private_data;
1754 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);