Lines Matching refs:WREG32

243 	WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
251 WREG32(base_reg + 0xE80, 0x80004);
252 WREG32(base_reg + 0xD64, 7);
253 WREG32(base_reg + 0xD60, 0);
254 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask));
255 WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask));
256 WREG32(base_reg + 0xD60, 1);
257 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask));
258 WREG32(base_reg + 0xD20, upper_32_bits(input->sp_mask));
259 WREG32(base_reg + 0xE70, 0x10);
260 WREG32(base_reg + 0xE60, 0);
261 WREG32(base_reg + 0xE64, 0x420000);
262 WREG32(base_reg + 0xE00, 0xFFFFFFFF);
263 WREG32(base_reg + 0xE20, 0xFFFFFFFF);
264 WREG32(base_reg + 0xEF4, input->id);
265 WREG32(base_reg + 0xDF4, 0x80);
269 WREG32(base_reg + 0xE8C, frequency);
270 WREG32(base_reg + 0xE90, 0x7FF);
271 WREG32(base_reg + 0xE80, 0x27 | (input->id << 16));
273 WREG32(base_reg + 0xE80, 4);
274 WREG32(base_reg + 0xD64, 0);
275 WREG32(base_reg + 0xD60, 1);
276 WREG32(base_reg + 0xD00, 0);
277 WREG32(base_reg + 0xD20, 0);
278 WREG32(base_reg + 0xD60, 0);
279 WREG32(base_reg + 0xE20, 0);
280 WREG32(base_reg + 0xE00, 0);
281 WREG32(base_reg + 0xDF4, 0x80);
282 WREG32(base_reg + 0xE70, 0);
283 WREG32(base_reg + 0xE60, 0);
284 WREG32(base_reg + 0xE64, 0);
285 WREG32(base_reg + 0xE8C, 0);
295 WREG32(base_reg + 0xE80, 4);
316 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
325 WREG32(base_reg + 0x304, val);
327 WREG32(base_reg + 0x304, val);
345 WREG32(base_reg + 0x20, 0);
353 WREG32(base_reg + 0x34, 0x3FFC);
354 WREG32(base_reg + 0x28, input->sink_mode);
355 WREG32(base_reg + 0x304, 0x4001);
356 WREG32(base_reg + 0x308, 0xA);
357 WREG32(base_reg + 0x20, 1);
359 WREG32(base_reg + 0x34, 0);
360 WREG32(base_reg + 0x28, 0);
361 WREG32(base_reg + 0x304, 0);
392 WREG32(mmPSOC_ETR_LAR, CORESIGHT_UNLOCK);
401 WREG32(mmPSOC_ETR_FFCR, val);
403 WREG32(mmPSOC_ETR_FFCR, val);
419 WREG32(mmPSOC_ETR_CTL, 0);
439 WREG32(mmPSOC_ETR_BUFWM, 0x3FFC);
440 WREG32(mmPSOC_ETR_RSZ, input->buffer_size);
441 WREG32(mmPSOC_ETR_MODE, input->sink_mode);
449 WREG32(mmPSOC_ETR_AXICTL, val);
451 WREG32(mmPSOC_ETR_DBALO,
453 WREG32(mmPSOC_ETR_DBAHI,
455 WREG32(mmPSOC_ETR_FFCR, 3);
456 WREG32(mmPSOC_ETR_PSCR, 0xA);
457 WREG32(mmPSOC_ETR_CTL, 1);
459 WREG32(mmPSOC_ETR_BUFWM, 0);
460 WREG32(mmPSOC_ETR_RSZ, 0x400);
461 WREG32(mmPSOC_ETR_DBALO, 0);
462 WREG32(mmPSOC_ETR_DBAHI, 0);
463 WREG32(mmPSOC_ETR_PSCR, 0);
464 WREG32(mmPSOC_ETR_MODE, 0);
465 WREG32(mmPSOC_ETR_FFCR, 0);
496 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
498 WREG32(base_reg, params->enable ? 0x33F : 0);
517 WREG32(base_reg + 0x104, 1);
525 WREG32(base_reg + 0x200, lower_32_bits(input->start_addr0));
526 WREG32(base_reg + 0x204, upper_32_bits(input->start_addr0));
527 WREG32(base_reg + 0x208, lower_32_bits(input->addr_mask0));
528 WREG32(base_reg + 0x20C, upper_32_bits(input->addr_mask0));
529 WREG32(base_reg + 0x240, lower_32_bits(input->start_addr1));
530 WREG32(base_reg + 0x244, upper_32_bits(input->start_addr1));
531 WREG32(base_reg + 0x248, lower_32_bits(input->addr_mask1));
532 WREG32(base_reg + 0x24C, upper_32_bits(input->addr_mask1));
533 WREG32(base_reg + 0x224, 0);
534 WREG32(base_reg + 0x234, 0);
535 WREG32(base_reg + 0x30C, input->bw_win);
536 WREG32(base_reg + 0x308, input->win_capture);
545 WREG32(base_reg + 0x700, pcie_base | 0xB00 | (input->id << 12));
546 WREG32(base_reg + 0x708, pcie_base | 0xA00 | (input->id << 12));
547 WREG32(base_reg + 0x70C, pcie_base | 0xC00 | (input->id << 12));
549 WREG32(base_reg + 0x100, 0x11);
550 WREG32(base_reg + 0x304, 0x1);
552 WREG32(base_reg + 0x200, 0);
553 WREG32(base_reg + 0x204, 0);
554 WREG32(base_reg + 0x208, 0xFFFFFFFF);
555 WREG32(base_reg + 0x20C, 0xFFFFFFFF);
556 WREG32(base_reg + 0x240, 0);
557 WREG32(base_reg + 0x244, 0);
558 WREG32(base_reg + 0x248, 0xFFFFFFFF);
559 WREG32(base_reg + 0x24C, 0xFFFFFFFF);
560 WREG32(base_reg + 0x224, 0xFFFFFFFF);
561 WREG32(base_reg + 0x234, 0x1070F);
562 WREG32(base_reg + 0x30C, 0);
563 WREG32(base_reg + 0x308, 0xFFFF);
564 WREG32(base_reg + 0x700, 0xA000B00);
565 WREG32(base_reg + 0x708, 0xA000A00);
566 WREG32(base_reg + 0x70C, 0xA000C00);
567 WREG32(base_reg + 0x100, 1);
568 WREG32(base_reg + 0x304, 0);
569 WREG32(base_reg + 0x104, 0);
611 WREG32(base_reg + 0xE04, 0x41013046);
612 WREG32(base_reg + 0xE04, 0x41013040);
615 WREG32(base_reg + SPMU_EVENT_TYPES_OFFSET + i * 4,
618 WREG32(base_reg + 0xE04, 0x41013041);
619 WREG32(base_reg + 0xC00, 0x8000003F);
642 WREG32(base_reg + 0xE04, 0x41013040);
653 WREG32(base_reg + 0xCC0, 0);