Lines Matching refs:WREG32
732 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED);
734 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED);
893 WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size));
1101 WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address));
1102 WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address));
1104 WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH));
1105 WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0);
1106 WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0);
1108 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1109 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1110 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1111 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1112 WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1113 WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1114 WREG32(mmDMA_QM_0_GLBL_ERR_WDATA + reg_off,
1118 WREG32(mmDMA_QM_0_PQ_CFG1 + reg_off, 0x00020002);
1119 WREG32(mmDMA_QM_0_CQ_CFG1 + reg_off, 0x00080008);
1122 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_PARTLY_TRUSTED);
1124 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_FULLY_TRUSTED);
1129 WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, dma_err_cfg);
1130 WREG32(mmDMA_QM_0_GLBL_CFG0 + reg_off, QMAN_DMA_ENABLE);
1144 WREG32(mmDMA_CH_0_ERRMSG_ADDR_LO + reg_off, gic_base_lo);
1145 WREG32(mmDMA_CH_0_ERRMSG_ADDR_HI + reg_off, gic_base_hi);
1146 WREG32(mmDMA_CH_0_ERRMSG_WDATA + reg_off,
1155 WREG32(mmDMA_CH_0_WR_COMP_ADDR_HI + reg_off, upper_32_bits(sob_addr));
1156 WREG32(mmDMA_CH_0_WR_COMP_WDATA + reg_off, 0x80000001);
1200 WREG32(mmDMA_QM_0_GLBL_CFG0, 0);
1201 WREG32(mmDMA_QM_1_GLBL_CFG0, 0);
1202 WREG32(mmDMA_QM_2_GLBL_CFG0, 0);
1203 WREG32(mmDMA_QM_3_GLBL_CFG0, 0);
1204 WREG32(mmDMA_QM_4_GLBL_CFG0, 0);
1215 WREG32(cfg_reg, 1 << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
1344 WREG32(mmCPU_PQ_BASE_ADDR_LOW, lower_32_bits(cpu_pq->bus_address));
1345 WREG32(mmCPU_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address));
1347 WREG32(mmCPU_EQ_BASE_ADDR_LOW, lower_32_bits(eq->bus_address));
1348 WREG32(mmCPU_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address));
1350 WREG32(mmCPU_CQ_BASE_ADDR_LOW,
1352 WREG32(mmCPU_CQ_BASE_ADDR_HIGH,
1355 WREG32(mmCPU_PQ_LENGTH, HL_QUEUE_SIZE_IN_BYTES);
1356 WREG32(mmCPU_EQ_LENGTH, HL_EQ_SIZE_IN_BYTES);
1357 WREG32(mmCPU_CQ_LENGTH, HL_CPU_ACCESSIBLE_MEM_SIZE);
1360 WREG32(mmCPU_EQ_CI, 0);
1362 WREG32(mmCPU_IF_PF_PQ_PI, 0);
1364 WREG32(mmCPU_PQ_INIT_STATUS, PQ_INIT_STATUS_READY_FOR_CP);
1366 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
1396 WREG32(mmCPU_PLL_DIV_SEL_0, 0x0);
1397 WREG32(mmCPU_PLL_DIV_SEL_1, 0x0);
1398 WREG32(mmCPU_PLL_DIV_SEL_2, 0x0);
1399 WREG32(mmCPU_PLL_DIV_SEL_3, 0x0);
1401 WREG32(mmIC_PLL_DIV_SEL_0, 0x0);
1402 WREG32(mmIC_PLL_DIV_SEL_1, 0x0);
1403 WREG32(mmIC_PLL_DIV_SEL_2, 0x0);
1404 WREG32(mmIC_PLL_DIV_SEL_3, 0x0);
1406 WREG32(mmMC_PLL_DIV_SEL_0, 0x0);
1407 WREG32(mmMC_PLL_DIV_SEL_1, 0x0);
1408 WREG32(mmMC_PLL_DIV_SEL_2, 0x0);
1409 WREG32(mmMC_PLL_DIV_SEL_3, 0x0);
1411 WREG32(mmPSOC_MME_PLL_DIV_SEL_0, 0x0);
1412 WREG32(mmPSOC_MME_PLL_DIV_SEL_1, 0x0);
1413 WREG32(mmPSOC_MME_PLL_DIV_SEL_2, 0x0);
1414 WREG32(mmPSOC_MME_PLL_DIV_SEL_3, 0x0);
1416 WREG32(mmPSOC_PCI_PLL_DIV_SEL_0, 0x0);
1417 WREG32(mmPSOC_PCI_PLL_DIV_SEL_1, 0x0);
1418 WREG32(mmPSOC_PCI_PLL_DIV_SEL_2, 0x0);
1419 WREG32(mmPSOC_PCI_PLL_DIV_SEL_3, 0x0);
1421 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_0, 0x0);
1422 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_1, 0x0);
1423 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_2, 0x0);
1424 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_3, 0x0);
1426 WREG32(mmTPC_PLL_DIV_SEL_0, 0x0);
1427 WREG32(mmTPC_PLL_DIV_SEL_1, 0x0);
1428 WREG32(mmTPC_PLL_DIV_SEL_2, 0x0);
1429 WREG32(mmTPC_PLL_DIV_SEL_3, 0x0);
1434 WREG32(mmPSOC_MME_PLL_CLK_RLX_0, 0x100010);
1435 WREG32(mmIC_PLL_CLK_RLX_0, 0x100010);
1459 WREG32(mmTPC0_CFG_FUNC_MBIST_PAT + tpc_offset, val & 0xFFFFF000);
1461 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_0 + tpc_offset, 0x37FF);
1462 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_1 + tpc_offset, 0x303F);
1463 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_2 + tpc_offset, 0x71FF);
1464 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_3 + tpc_offset, 0x71FF);
1465 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_4 + tpc_offset, 0x70FF);
1466 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_5 + tpc_offset, 0x70FF);
1467 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_6 + tpc_offset, 0x70FF);
1468 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_7 + tpc_offset, 0x70FF);
1469 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_8 + tpc_offset, 0x70FF);
1470 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_9 + tpc_offset, 0x70FF);
1498 WREG32(tpc_slm_offset + (slm_index << 2), 0);
1554 WREG32(mmSRAM_Y0_X0_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1555 WREG32(mmSRAM_Y0_X1_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1556 WREG32(mmSRAM_Y0_X2_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1557 WREG32(mmSRAM_Y0_X3_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1558 WREG32(mmSRAM_Y0_X4_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1560 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_L_ARB + offset, 0x204);
1561 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_L_ARB + offset, 0x204);
1562 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_L_ARB + offset, 0x204);
1563 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_L_ARB + offset, 0x204);
1564 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_L_ARB + offset, 0x204);
1567 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_E_ARB + offset, 0x206);
1568 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_E_ARB + offset, 0x206);
1569 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_E_ARB + offset, 0x206);
1570 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_E_ARB + offset, 0x207);
1571 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_E_ARB + offset, 0x207);
1573 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_W_ARB + offset, 0x207);
1574 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_W_ARB + offset, 0x207);
1575 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_W_ARB + offset, 0x206);
1576 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_W_ARB + offset, 0x206);
1577 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_W_ARB + offset, 0x206);
1579 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_E_ARB + offset, 0x101);
1580 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_E_ARB + offset, 0x102);
1581 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_E_ARB + offset, 0x103);
1582 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_E_ARB + offset, 0x104);
1583 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_E_ARB + offset, 0x105);
1585 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_W_ARB + offset, 0x105);
1586 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_W_ARB + offset, 0x104);
1587 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_W_ARB + offset, 0x103);
1588 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_W_ARB + offset, 0x102);
1589 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_W_ARB + offset, 0x101);
1592 WREG32(mmMME_STORE_MAX_CREDIT, 0x21);
1593 WREG32(mmMME_AGU, 0x0f0f0f10);
1594 WREG32(mmMME_SEI_MASK, ~0x0);
1596 WREG32(mmMME6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1597 WREG32(mmMME5_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1598 WREG32(mmMME4_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1599 WREG32(mmMME3_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1600 WREG32(mmMME2_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1601 WREG32(mmMME1_RTR_HBW_RD_RQ_N_ARB, 0x07010701);
1602 WREG32(mmMME6_RTR_HBW_RD_RQ_S_ARB, 0x04010401);
1603 WREG32(mmMME5_RTR_HBW_RD_RQ_S_ARB, 0x04050401);
1604 WREG32(mmMME4_RTR_HBW_RD_RQ_S_ARB, 0x03070301);
1605 WREG32(mmMME3_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1606 WREG32(mmMME2_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1607 WREG32(mmMME1_RTR_HBW_RD_RQ_S_ARB, 0x01050105);
1608 WREG32(mmMME6_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1609 WREG32(mmMME5_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1610 WREG32(mmMME4_RTR_HBW_RD_RQ_W_ARB, 0x01040301);
1611 WREG32(mmMME3_RTR_HBW_RD_RQ_W_ARB, 0x01030401);
1612 WREG32(mmMME2_RTR_HBW_RD_RQ_W_ARB, 0x01040101);
1613 WREG32(mmMME1_RTR_HBW_RD_RQ_W_ARB, 0x01050101);
1614 WREG32(mmMME6_RTR_HBW_WR_RQ_N_ARB, 0x02020202);
1615 WREG32(mmMME5_RTR_HBW_WR_RQ_N_ARB, 0x01070101);
1616 WREG32(mmMME4_RTR_HBW_WR_RQ_N_ARB, 0x02020201);
1617 WREG32(mmMME3_RTR_HBW_WR_RQ_N_ARB, 0x07020701);
1618 WREG32(mmMME2_RTR_HBW_WR_RQ_N_ARB, 0x01020101);
1619 WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1620 WREG32(mmMME6_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1621 WREG32(mmMME5_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1622 WREG32(mmMME4_RTR_HBW_WR_RQ_S_ARB, 0x07020701);
1623 WREG32(mmMME3_RTR_HBW_WR_RQ_S_ARB, 0x02020201);
1624 WREG32(mmMME2_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1625 WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01020102);
1626 WREG32(mmMME6_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1627 WREG32(mmMME5_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1628 WREG32(mmMME4_RTR_HBW_WR_RQ_W_ARB, 0x07020707);
1629 WREG32(mmMME3_RTR_HBW_WR_RQ_W_ARB, 0x01020201);
1630 WREG32(mmMME2_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1631 WREG32(mmMME1_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1632 WREG32(mmMME6_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1633 WREG32(mmMME5_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1634 WREG32(mmMME4_RTR_HBW_RD_RS_N_ARB, 0x01060102);
1635 WREG32(mmMME3_RTR_HBW_RD_RS_N_ARB, 0x01040102);
1636 WREG32(mmMME2_RTR_HBW_RD_RS_N_ARB, 0x01020102);
1637 WREG32(mmMME1_RTR_HBW_RD_RS_N_ARB, 0x01020107);
1638 WREG32(mmMME6_RTR_HBW_RD_RS_S_ARB, 0x01020106);
1639 WREG32(mmMME5_RTR_HBW_RD_RS_S_ARB, 0x01020102);
1640 WREG32(mmMME4_RTR_HBW_RD_RS_S_ARB, 0x01040102);
1641 WREG32(mmMME3_RTR_HBW_RD_RS_S_ARB, 0x01060102);
1642 WREG32(mmMME2_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1643 WREG32(mmMME1_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1644 WREG32(mmMME6_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1645 WREG32(mmMME5_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1646 WREG32(mmMME4_RTR_HBW_RD_RS_E_ARB, 0x01040602);
1647 WREG32(mmMME3_RTR_HBW_RD_RS_E_ARB, 0x01060402);
1648 WREG32(mmMME2_RTR_HBW_RD_RS_E_ARB, 0x01070202);
1649 WREG32(mmMME1_RTR_HBW_RD_RS_E_ARB, 0x01070102);
1650 WREG32(mmMME6_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1651 WREG32(mmMME5_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1652 WREG32(mmMME4_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1653 WREG32(mmMME3_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1654 WREG32(mmMME2_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1655 WREG32(mmMME1_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1656 WREG32(mmMME6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1657 WREG32(mmMME5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1658 WREG32(mmMME4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1659 WREG32(mmMME3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1660 WREG32(mmMME2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1661 WREG32(mmMME1_RTR_HBW_WR_RS_N_ARB, 0x01010107);
1662 WREG32(mmMME6_RTR_HBW_WR_RS_S_ARB, 0x01010107);
1663 WREG32(mmMME5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1664 WREG32(mmMME4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1665 WREG32(mmMME3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1666 WREG32(mmMME2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1667 WREG32(mmMME1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1668 WREG32(mmMME6_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1669 WREG32(mmMME5_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1670 WREG32(mmMME4_RTR_HBW_WR_RS_E_ARB, 0x01040301);
1671 WREG32(mmMME3_RTR_HBW_WR_RS_E_ARB, 0x01030401);
1672 WREG32(mmMME2_RTR_HBW_WR_RS_E_ARB, 0x01040101);
1673 WREG32(mmMME1_RTR_HBW_WR_RS_E_ARB, 0x01050101);
1674 WREG32(mmMME6_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1675 WREG32(mmMME5_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1676 WREG32(mmMME4_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1677 WREG32(mmMME3_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1678 WREG32(mmMME2_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1679 WREG32(mmMME1_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1681 WREG32(mmTPC1_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1682 WREG32(mmTPC1_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1683 WREG32(mmTPC1_RTR_HBW_RD_RQ_E_ARB, 0x01060101);
1684 WREG32(mmTPC1_RTR_HBW_WR_RQ_N_ARB, 0x02020102);
1685 WREG32(mmTPC1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1686 WREG32(mmTPC1_RTR_HBW_WR_RQ_E_ARB, 0x02070202);
1687 WREG32(mmTPC1_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1688 WREG32(mmTPC1_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1689 WREG32(mmTPC1_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1690 WREG32(mmTPC1_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1691 WREG32(mmTPC1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1692 WREG32(mmTPC1_RTR_HBW_WR_RS_W_ARB, 0x01050101);
1694 WREG32(mmTPC2_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1695 WREG32(mmTPC2_RTR_HBW_RD_RQ_S_ARB, 0x01050101);
1696 WREG32(mmTPC2_RTR_HBW_RD_RQ_E_ARB, 0x01010201);
1697 WREG32(mmTPC2_RTR_HBW_WR_RQ_N_ARB, 0x02040102);
1698 WREG32(mmTPC2_RTR_HBW_WR_RQ_S_ARB, 0x01050101);
1699 WREG32(mmTPC2_RTR_HBW_WR_RQ_E_ARB, 0x02060202);
1700 WREG32(mmTPC2_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1701 WREG32(mmTPC2_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1702 WREG32(mmTPC2_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1703 WREG32(mmTPC2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1704 WREG32(mmTPC2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1705 WREG32(mmTPC2_RTR_HBW_WR_RS_W_ARB, 0x01040101);
1707 WREG32(mmTPC3_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1708 WREG32(mmTPC3_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1709 WREG32(mmTPC3_RTR_HBW_RD_RQ_E_ARB, 0x01040301);
1710 WREG32(mmTPC3_RTR_HBW_WR_RQ_N_ARB, 0x02060102);
1711 WREG32(mmTPC3_RTR_HBW_WR_RQ_S_ARB, 0x01040101);
1712 WREG32(mmTPC3_RTR_HBW_WR_RQ_E_ARB, 0x01040301);
1713 WREG32(mmTPC3_RTR_HBW_RD_RS_N_ARB, 0x01040201);
1714 WREG32(mmTPC3_RTR_HBW_RD_RS_S_ARB, 0x01060201);
1715 WREG32(mmTPC3_RTR_HBW_RD_RS_W_ARB, 0x01060402);
1716 WREG32(mmTPC3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1717 WREG32(mmTPC3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1718 WREG32(mmTPC3_RTR_HBW_WR_RS_W_ARB, 0x01030401);
1720 WREG32(mmTPC4_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1721 WREG32(mmTPC4_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1722 WREG32(mmTPC4_RTR_HBW_RD_RQ_E_ARB, 0x01030401);
1723 WREG32(mmTPC4_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1724 WREG32(mmTPC4_RTR_HBW_WR_RQ_S_ARB, 0x01030101);
1725 WREG32(mmTPC4_RTR_HBW_WR_RQ_E_ARB, 0x02060702);
1726 WREG32(mmTPC4_RTR_HBW_RD_RS_N_ARB, 0x01060201);
1727 WREG32(mmTPC4_RTR_HBW_RD_RS_S_ARB, 0x01040201);
1728 WREG32(mmTPC4_RTR_HBW_RD_RS_W_ARB, 0x01040602);
1729 WREG32(mmTPC4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1730 WREG32(mmTPC4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1731 WREG32(mmTPC4_RTR_HBW_WR_RS_W_ARB, 0x01040301);
1733 WREG32(mmTPC5_RTR_HBW_RD_RQ_N_ARB, 0x01050101);
1734 WREG32(mmTPC5_RTR_HBW_RD_RQ_S_ARB, 0x01020101);
1735 WREG32(mmTPC5_RTR_HBW_RD_RQ_E_ARB, 0x01200501);
1736 WREG32(mmTPC5_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1737 WREG32(mmTPC5_RTR_HBW_WR_RQ_S_ARB, 0x01020101);
1738 WREG32(mmTPC5_RTR_HBW_WR_RQ_E_ARB, 0x02020602);
1739 WREG32(mmTPC5_RTR_HBW_RD_RS_N_ARB, 0x01070201);
1740 WREG32(mmTPC5_RTR_HBW_RD_RS_S_ARB, 0x01020201);
1741 WREG32(mmTPC5_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1742 WREG32(mmTPC5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1743 WREG32(mmTPC5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1744 WREG32(mmTPC5_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1746 WREG32(mmTPC6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1747 WREG32(mmTPC6_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1748 WREG32(mmTPC6_RTR_HBW_RD_RQ_E_ARB, 0x01010601);
1749 WREG32(mmTPC6_RTR_HBW_WR_RQ_N_ARB, 0x01010101);
1750 WREG32(mmTPC6_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1751 WREG32(mmTPC6_RTR_HBW_WR_RQ_E_ARB, 0x02020702);
1752 WREG32(mmTPC6_RTR_HBW_RD_RS_N_ARB, 0x01010101);
1753 WREG32(mmTPC6_RTR_HBW_RD_RS_S_ARB, 0x01010101);
1754 WREG32(mmTPC6_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1755 WREG32(mmTPC6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1756 WREG32(mmTPC6_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1757 WREG32(mmTPC6_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1760 WREG32(mmMME1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1761 WREG32(mmMME2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1762 WREG32(mmMME3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1763 WREG32(mmMME4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1764 WREG32(mmMME5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1765 WREG32(mmMME6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1767 WREG32(mmTPC0_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1768 WREG32(mmTPC1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1769 WREG32(mmTPC2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1770 WREG32(mmTPC3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1771 WREG32(mmTPC4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1772 WREG32(mmTPC5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1773 WREG32(mmTPC6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1774 WREG32(mmTPC7_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1776 WREG32(mmPCI_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1777 WREG32(mmDMA_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1781 WREG32(mmMME1_RTR_SCRAMB_EN + offset,
1783 WREG32(mmMME1_RTR_NON_LIN_SCRAMB + offset,
1792 WREG32(mmTPC0_CFG_TPC_INTR_MASK + offset, tpc_intr_mask);
1794 WREG32(mmTPC0_NRTR_SCRAMB_EN + offset,
1796 WREG32(mmTPC0_NRTR_NON_LIN_SCRAMB + offset,
1803 WREG32(mmDMA_NRTR_SCRAMB_EN, 1 << DMA_NRTR_SCRAMB_EN_VAL_SHIFT);
1804 WREG32(mmDMA_NRTR_NON_LIN_SCRAMB,
1807 WREG32(mmPCI_NRTR_SCRAMB_EN, 1 << PCI_NRTR_SCRAMB_EN_VAL_SHIFT);
1808 WREG32(mmPCI_NRTR_NON_LIN_SCRAMB,
1818 WREG32(mmDMA_CH_1_CFG0, 0x0fff00F0);
1820 WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
1845 WREG32(mmMME_QM_PQ_BASE_LO, lower_32_bits(qman_base_addr));
1846 WREG32(mmMME_QM_PQ_BASE_HI, upper_32_bits(qman_base_addr));
1847 WREG32(mmMME_QM_PQ_SIZE, ilog2(MME_QMAN_LENGTH));
1848 WREG32(mmMME_QM_PQ_PI, 0);
1849 WREG32(mmMME_QM_PQ_CI, 0);
1850 WREG32(mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET, 0x10C0);
1851 WREG32(mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET, 0x10C4);
1852 WREG32(mmMME_QM_CP_LDMA_TSIZE_OFFSET, 0x10C8);
1853 WREG32(mmMME_QM_CP_LDMA_COMMIT_OFFSET, 0x10CC);
1855 WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1856 WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1857 WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1858 WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1861 WREG32(mmMME_QM_CQ_CFG1, 0x00080008);
1863 WREG32(mmMME_QM_GLBL_ERR_ADDR_LO, gic_base_lo);
1864 WREG32(mmMME_QM_GLBL_ERR_ADDR_HI, gic_base_hi);
1866 WREG32(mmMME_QM_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_QM);
1868 WREG32(mmMME_QM_GLBL_ERR_CFG, QMAN_MME_ERR_MSG_EN);
1870 WREG32(mmMME_QM_GLBL_PROT, QMAN_MME_ERR_PROT);
1872 WREG32(mmMME_QM_GLBL_CFG0, QMAN_MME_ENABLE);
1891 WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1892 WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1893 WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1894 WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1897 WREG32(mmMME_CMDQ_CQ_CFG1, 0x00140014);
1899 WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_LO, gic_base_lo);
1900 WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_HI, gic_base_hi);
1902 WREG32(mmMME_CMDQ_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_CMDQ);
1904 WREG32(mmMME_CMDQ_GLBL_ERR_CFG, CMDQ_MME_ERR_MSG_EN);
1906 WREG32(mmMME_CMDQ_GLBL_PROT, CMDQ_MME_ERR_PROT);
1908 WREG32(mmMME_CMDQ_GLBL_CFG0, CMDQ_MME_ENABLE);
1922 WREG32(mmMME_SM_BASE_ADDRESS_LOW, so_base_lo);
1923 WREG32(mmMME_SM_BASE_ADDRESS_HIGH, so_base_hi);
1951 WREG32(mmTPC0_QM_PQ_BASE_LO + reg_off, lower_32_bits(qman_base_addr));
1952 WREG32(mmTPC0_QM_PQ_BASE_HI + reg_off, upper_32_bits(qman_base_addr));
1953 WREG32(mmTPC0_QM_PQ_SIZE + reg_off, ilog2(TPC_QMAN_LENGTH));
1954 WREG32(mmTPC0_QM_PQ_PI + reg_off, 0);
1955 WREG32(mmTPC0_QM_PQ_CI + reg_off, 0);
1956 WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET + reg_off, 0x10C0);
1957 WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET + reg_off, 0x10C4);
1958 WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET + reg_off, 0x10C8);
1959 WREG32(mmTPC0_QM_CP_LDMA_COMMIT_OFFSET + reg_off, 0x10CC);
1961 WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1962 WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1963 WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1964 WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1966 WREG32(mmTPC0_QM_CQ_CFG1 + reg_off, 0x00080008);
1968 WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1969 WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1971 WREG32(mmTPC0_QM_GLBL_ERR_WDATA + reg_off,
1974 WREG32(mmTPC0_QM_GLBL_ERR_CFG + reg_off, QMAN_TPC_ERR_MSG_EN);
1976 WREG32(mmTPC0_QM_GLBL_PROT + reg_off, QMAN_TPC_ERR_PROT);
1978 WREG32(mmTPC0_QM_GLBL_CFG0 + reg_off, QMAN_TPC_ENABLE);
1998 WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1999 WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
2000 WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
2001 WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
2003 WREG32(mmTPC0_CMDQ_CQ_CFG1 + reg_off, 0x00140014);
2005 WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
2006 WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
2008 WREG32(mmTPC0_CMDQ_GLBL_ERR_WDATA + reg_off,
2011 WREG32(mmTPC0_CMDQ_GLBL_ERR_CFG + reg_off, CMDQ_TPC_ERR_MSG_EN);
2013 WREG32(mmTPC0_CMDQ_GLBL_PROT + reg_off, CMDQ_TPC_ERR_PROT);
2015 WREG32(mmTPC0_CMDQ_GLBL_CFG0 + reg_off, CMDQ_TPC_ENABLE);
2033 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_LOW + i * cfg_off,
2035 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + i * cfg_off,
2067 WREG32(mmMME_QM_GLBL_CFG0, 0);
2068 WREG32(mmMME_CMDQ_GLBL_CFG0, 0);
2074 WREG32(mmTPC0_QM_GLBL_CFG0, 0);
2075 WREG32(mmTPC0_CMDQ_GLBL_CFG0, 0);
2077 WREG32(mmTPC1_QM_GLBL_CFG0, 0);
2078 WREG32(mmTPC1_CMDQ_GLBL_CFG0, 0);
2080 WREG32(mmTPC2_QM_GLBL_CFG0, 0);
2081 WREG32(mmTPC2_CMDQ_GLBL_CFG0, 0);
2083 WREG32(mmTPC3_QM_GLBL_CFG0, 0);
2084 WREG32(mmTPC3_CMDQ_GLBL_CFG0, 0);
2086 WREG32(mmTPC4_QM_GLBL_CFG0, 0);
2087 WREG32(mmTPC4_CMDQ_GLBL_CFG0, 0);
2089 WREG32(mmTPC5_QM_GLBL_CFG0, 0);
2090 WREG32(mmTPC5_CMDQ_GLBL_CFG0, 0);
2092 WREG32(mmTPC6_QM_GLBL_CFG0, 0);
2093 WREG32(mmTPC6_CMDQ_GLBL_CFG0, 0);
2095 WREG32(mmTPC7_QM_GLBL_CFG0, 0);
2096 WREG32(mmTPC7_CMDQ_GLBL_CFG0, 0);
2315 WREG32(mmDMA_QM_0_GLBL_CFG1, 1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT);
2316 WREG32(mmDMA_QM_1_GLBL_CFG1, 1 << DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT);
2317 WREG32(mmDMA_QM_2_GLBL_CFG1, 1 << DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT);
2318 WREG32(mmDMA_QM_3_GLBL_CFG1, 1 << DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT);
2319 WREG32(mmDMA_QM_4_GLBL_CFG1, 1 << DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT);
2329 WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
2330 WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC1_CFG_TPC_STALL_V_SHIFT);
2331 WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC2_CFG_TPC_STALL_V_SHIFT);
2332 WREG32(mmTPC3_CFG_TPC_STALL, 1 << TPC3_CFG_TPC_STALL_V_SHIFT);
2333 WREG32(mmTPC4_CFG_TPC_STALL, 1 << TPC4_CFG_TPC_STALL_V_SHIFT);
2334 WREG32(mmTPC5_CFG_TPC_STALL, 1 << TPC5_CFG_TPC_STALL_V_SHIFT);
2335 WREG32(mmTPC6_CFG_TPC_STALL, 1 << TPC6_CFG_TPC_STALL_V_SHIFT);
2336 WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC7_CFG_TPC_STALL_V_SHIFT);
2346 WREG32(mmMME_STALL, 0xFFFFFFFF);
2440 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
2443 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0xC, 0);
2444 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0x8, 0);
2447 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 1);
2453 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
2641 WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT);
2642 WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT);
2643 WREG32(MMU_ASID_BUSY, 0x80000000 | asid);
2689 WREG32(mmSTLB_CACHE_INV_BASE_39_8,
2691 WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR >> 40);
2699 WREG32(mmMMU_MMU_ENABLE, 1);
2700 WREG32(mmMMU_SPI_MASK, 0xF);
2730 WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY);
2801 WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_GOTO_WFE);
2802 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2811 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, RESET_ALL);
2816 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, DMA_MME_TPC_RESET);
2838 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2844 WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START,
2847 WREG32(mmPSOC_GLOBAL_CONF_SW_BTM_FSM,
2963 WREG32(db_reg_offset, db_value);
2968 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
3606 dev_dbg(hdev->dev, "WREG32 packet details:\n");
3612 dev_err(hdev->dev, "WREG32 packet with illegal address 0x%x\n",
3631 dev_err(hdev->dev, "WREG32 packet with illegal value 0x%x\n",
4168 WREG32(mmCPU_EQ_CI, val);
4187 WREG32(mmSYNC_MNGR_SOB_OBJ_0 + i, 0);
4190 WREG32(mmSYNC_MNGR_MON_STATUS_0 + i, 0);
4426 WREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD, 0);
4431 WREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD, 0);
4436 WREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD, 0);
4441 WREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD, 0);
4463 WREG32(mmMMU_PAGE_ERROR_CAPTURE, 0);
4844 WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO, lower_32_bits(sob_addr));
4849 WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO + channel_off * dma_id,
4853 WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
4938 WREG32(mmCPU_IF_ARUSER_OVR_EN, 0x7FF);
4939 WREG32(mmCPU_IF_AWUSER_OVR_EN, 0x7FF);
4980 WREG32(mmCPU_IF_ARUSER_OVR_EN, 0);
4981 WREG32(mmCPU_IF_AWUSER_OVR_EN, 0);
5050 WREG32(mmSTLB_INV_ALL_START, 1);
5324 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,