Lines Matching refs:WREG32
1132 WREG32((mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 +
1627 WREG32(mmNIC0_QM0_GLBL_CFG1, NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
1631 WREG32(mmNIC0_QM1_GLBL_CFG1, NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
1635 WREG32(mmNIC0_QM0_GLBL_CFG0, 0);
1636 WREG32(mmNIC0_QM1_GLBL_CFG0, 0);
2082 WREG32(mmNIF_RTR_CTRL_0_SCRAM_SRAM_EN,
2084 WREG32(mmNIF_RTR_CTRL_1_SCRAM_SRAM_EN,
2086 WREG32(mmNIF_RTR_CTRL_2_SCRAM_SRAM_EN,
2088 WREG32(mmNIF_RTR_CTRL_3_SCRAM_SRAM_EN,
2090 WREG32(mmNIF_RTR_CTRL_4_SCRAM_SRAM_EN,
2092 WREG32(mmNIF_RTR_CTRL_5_SCRAM_SRAM_EN,
2094 WREG32(mmNIF_RTR_CTRL_6_SCRAM_SRAM_EN,
2096 WREG32(mmNIF_RTR_CTRL_7_SCRAM_SRAM_EN,
2099 WREG32(mmSIF_RTR_CTRL_0_SCRAM_SRAM_EN,
2101 WREG32(mmSIF_RTR_CTRL_1_SCRAM_SRAM_EN,
2103 WREG32(mmSIF_RTR_CTRL_2_SCRAM_SRAM_EN,
2105 WREG32(mmSIF_RTR_CTRL_3_SCRAM_SRAM_EN,
2107 WREG32(mmSIF_RTR_CTRL_4_SCRAM_SRAM_EN,
2109 WREG32(mmSIF_RTR_CTRL_5_SCRAM_SRAM_EN,
2111 WREG32(mmSIF_RTR_CTRL_6_SCRAM_SRAM_EN,
2113 WREG32(mmSIF_RTR_CTRL_7_SCRAM_SRAM_EN,
2116 WREG32(mmDMA_IF_E_N_DOWN_CH0_SCRAM_SRAM_EN,
2118 WREG32(mmDMA_IF_E_N_DOWN_CH1_SCRAM_SRAM_EN,
2120 WREG32(mmDMA_IF_E_S_DOWN_CH0_SCRAM_SRAM_EN,
2122 WREG32(mmDMA_IF_E_S_DOWN_CH1_SCRAM_SRAM_EN,
2124 WREG32(mmDMA_IF_W_N_DOWN_CH0_SCRAM_SRAM_EN,
2126 WREG32(mmDMA_IF_W_N_DOWN_CH1_SCRAM_SRAM_EN,
2128 WREG32(mmDMA_IF_W_S_DOWN_CH0_SCRAM_SRAM_EN,
2130 WREG32(mmDMA_IF_W_S_DOWN_CH1_SCRAM_SRAM_EN,
2150 WREG32(mmNIF_RTR_CTRL_0_SCRAM_HBM_EN,
2152 WREG32(mmNIF_RTR_CTRL_1_SCRAM_HBM_EN,
2154 WREG32(mmNIF_RTR_CTRL_2_SCRAM_HBM_EN,
2156 WREG32(mmNIF_RTR_CTRL_3_SCRAM_HBM_EN,
2158 WREG32(mmNIF_RTR_CTRL_4_SCRAM_HBM_EN,
2160 WREG32(mmNIF_RTR_CTRL_5_SCRAM_HBM_EN,
2162 WREG32(mmNIF_RTR_CTRL_6_SCRAM_HBM_EN,
2164 WREG32(mmNIF_RTR_CTRL_7_SCRAM_HBM_EN,
2167 WREG32(mmSIF_RTR_CTRL_0_SCRAM_HBM_EN,
2169 WREG32(mmSIF_RTR_CTRL_1_SCRAM_HBM_EN,
2171 WREG32(mmSIF_RTR_CTRL_2_SCRAM_HBM_EN,
2173 WREG32(mmSIF_RTR_CTRL_3_SCRAM_HBM_EN,
2175 WREG32(mmSIF_RTR_CTRL_4_SCRAM_HBM_EN,
2177 WREG32(mmSIF_RTR_CTRL_5_SCRAM_HBM_EN,
2179 WREG32(mmSIF_RTR_CTRL_6_SCRAM_HBM_EN,
2181 WREG32(mmSIF_RTR_CTRL_7_SCRAM_HBM_EN,
2184 WREG32(mmDMA_IF_E_N_DOWN_CH0_SCRAM_HBM_EN,
2186 WREG32(mmDMA_IF_E_N_DOWN_CH1_SCRAM_HBM_EN,
2188 WREG32(mmDMA_IF_E_S_DOWN_CH0_SCRAM_HBM_EN,
2190 WREG32(mmDMA_IF_E_S_DOWN_CH1_SCRAM_HBM_EN,
2192 WREG32(mmDMA_IF_W_N_DOWN_CH0_SCRAM_HBM_EN,
2194 WREG32(mmDMA_IF_W_N_DOWN_CH1_SCRAM_HBM_EN,
2196 WREG32(mmDMA_IF_W_S_DOWN_CH0_SCRAM_HBM_EN,
2198 WREG32(mmDMA_IF_W_S_DOWN_CH1_SCRAM_HBM_EN,
2213 WREG32(mmSIF_RTR_CTRL_0_E2E_HBM_WR_SIZE, 247 >> 3);
2214 WREG32(mmSIF_RTR_CTRL_0_E2E_HBM_RD_SIZE, 785 >> 3);
2215 WREG32(mmSIF_RTR_CTRL_0_E2E_PCI_WR_SIZE, 49);
2216 WREG32(mmSIF_RTR_CTRL_0_E2E_PCI_RD_SIZE, 101);
2218 WREG32(mmSIF_RTR_CTRL_1_E2E_HBM_WR_SIZE, 275 >> 3);
2219 WREG32(mmSIF_RTR_CTRL_1_E2E_HBM_RD_SIZE, 614 >> 3);
2220 WREG32(mmSIF_RTR_CTRL_1_E2E_PCI_WR_SIZE, 1);
2221 WREG32(mmSIF_RTR_CTRL_1_E2E_PCI_RD_SIZE, 39);
2223 WREG32(mmSIF_RTR_CTRL_2_E2E_HBM_WR_SIZE, 1);
2224 WREG32(mmSIF_RTR_CTRL_2_E2E_HBM_RD_SIZE, 1);
2225 WREG32(mmSIF_RTR_CTRL_2_E2E_PCI_WR_SIZE, 1);
2226 WREG32(mmSIF_RTR_CTRL_2_E2E_PCI_RD_SIZE, 32);
2228 WREG32(mmSIF_RTR_CTRL_3_E2E_HBM_WR_SIZE, 176 >> 3);
2229 WREG32(mmSIF_RTR_CTRL_3_E2E_HBM_RD_SIZE, 32 >> 3);
2230 WREG32(mmSIF_RTR_CTRL_3_E2E_PCI_WR_SIZE, 19);
2231 WREG32(mmSIF_RTR_CTRL_3_E2E_PCI_RD_SIZE, 32);
2233 WREG32(mmSIF_RTR_CTRL_4_E2E_HBM_WR_SIZE, 176 >> 3);
2234 WREG32(mmSIF_RTR_CTRL_4_E2E_HBM_RD_SIZE, 32 >> 3);
2235 WREG32(mmSIF_RTR_CTRL_4_E2E_PCI_WR_SIZE, 19);
2236 WREG32(mmSIF_RTR_CTRL_4_E2E_PCI_RD_SIZE, 32);
2238 WREG32(mmSIF_RTR_CTRL_5_E2E_HBM_WR_SIZE, 1);
2239 WREG32(mmSIF_RTR_CTRL_5_E2E_HBM_RD_SIZE, 1);
2240 WREG32(mmSIF_RTR_CTRL_5_E2E_PCI_WR_SIZE, 1);
2241 WREG32(mmSIF_RTR_CTRL_5_E2E_PCI_RD_SIZE, 32);
2243 WREG32(mmSIF_RTR_CTRL_6_E2E_HBM_WR_SIZE, 275 >> 3);
2244 WREG32(mmSIF_RTR_CTRL_6_E2E_HBM_RD_SIZE, 614 >> 3);
2245 WREG32(mmSIF_RTR_CTRL_6_E2E_PCI_WR_SIZE, 1);
2246 WREG32(mmSIF_RTR_CTRL_6_E2E_PCI_RD_SIZE, 39);
2248 WREG32(mmSIF_RTR_CTRL_7_E2E_HBM_WR_SIZE, 297 >> 3);
2249 WREG32(mmSIF_RTR_CTRL_7_E2E_HBM_RD_SIZE, 908 >> 3);
2250 WREG32(mmSIF_RTR_CTRL_7_E2E_PCI_WR_SIZE, 19);
2251 WREG32(mmSIF_RTR_CTRL_7_E2E_PCI_RD_SIZE, 19);
2253 WREG32(mmNIF_RTR_CTRL_0_E2E_HBM_WR_SIZE, 318 >> 3);
2254 WREG32(mmNIF_RTR_CTRL_0_E2E_HBM_RD_SIZE, 956 >> 3);
2255 WREG32(mmNIF_RTR_CTRL_0_E2E_PCI_WR_SIZE, 79);
2256 WREG32(mmNIF_RTR_CTRL_0_E2E_PCI_RD_SIZE, 163);
2258 WREG32(mmNIF_RTR_CTRL_1_E2E_HBM_WR_SIZE, 275 >> 3);
2259 WREG32(mmNIF_RTR_CTRL_1_E2E_HBM_RD_SIZE, 614 >> 3);
2260 WREG32(mmNIF_RTR_CTRL_1_E2E_PCI_WR_SIZE, 1);
2261 WREG32(mmNIF_RTR_CTRL_1_E2E_PCI_RD_SIZE, 39);
2263 WREG32(mmNIF_RTR_CTRL_2_E2E_HBM_WR_SIZE, 1);
2264 WREG32(mmNIF_RTR_CTRL_2_E2E_HBM_RD_SIZE, 1);
2265 WREG32(mmNIF_RTR_CTRL_2_E2E_PCI_WR_SIZE, 1);
2266 WREG32(mmNIF_RTR_CTRL_2_E2E_PCI_RD_SIZE, 32);
2268 WREG32(mmNIF_RTR_CTRL_3_E2E_HBM_WR_SIZE, 176 >> 3);
2269 WREG32(mmNIF_RTR_CTRL_3_E2E_HBM_RD_SIZE, 32 >> 3);
2270 WREG32(mmNIF_RTR_CTRL_3_E2E_PCI_WR_SIZE, 19);
2271 WREG32(mmNIF_RTR_CTRL_3_E2E_PCI_RD_SIZE, 32);
2273 WREG32(mmNIF_RTR_CTRL_4_E2E_HBM_WR_SIZE, 176 >> 3);
2274 WREG32(mmNIF_RTR_CTRL_4_E2E_HBM_RD_SIZE, 32 >> 3);
2275 WREG32(mmNIF_RTR_CTRL_4_E2E_PCI_WR_SIZE, 19);
2276 WREG32(mmNIF_RTR_CTRL_4_E2E_PCI_RD_SIZE, 32);
2278 WREG32(mmNIF_RTR_CTRL_5_E2E_HBM_WR_SIZE, 1);
2279 WREG32(mmNIF_RTR_CTRL_5_E2E_HBM_RD_SIZE, 1);
2280 WREG32(mmNIF_RTR_CTRL_5_E2E_PCI_WR_SIZE, 1);
2281 WREG32(mmNIF_RTR_CTRL_5_E2E_PCI_RD_SIZE, 32);
2283 WREG32(mmNIF_RTR_CTRL_6_E2E_HBM_WR_SIZE, 275 >> 3);
2284 WREG32(mmNIF_RTR_CTRL_6_E2E_HBM_RD_SIZE, 614 >> 3);
2285 WREG32(mmNIF_RTR_CTRL_6_E2E_PCI_WR_SIZE, 1);
2286 WREG32(mmNIF_RTR_CTRL_6_E2E_PCI_RD_SIZE, 39);
2288 WREG32(mmNIF_RTR_CTRL_7_E2E_HBM_WR_SIZE, 318 >> 3);
2289 WREG32(mmNIF_RTR_CTRL_7_E2E_HBM_RD_SIZE, 956 >> 3);
2290 WREG32(mmNIF_RTR_CTRL_7_E2E_PCI_WR_SIZE, 79);
2291 WREG32(mmNIF_RTR_CTRL_7_E2E_PCI_RD_SIZE, 79);
2293 WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3);
2294 WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3);
2295 WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_WR_SIZE, 162);
2296 WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_RD_SIZE, 338);
2298 WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3);
2299 WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3);
2300 WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_WR_SIZE, 162);
2301 WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_RD_SIZE, 338);
2303 WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3);
2304 WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3);
2305 WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_WR_SIZE, 162);
2306 WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_RD_SIZE, 338);
2308 WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3);
2309 WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3);
2310 WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_WR_SIZE, 162);
2311 WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_RD_SIZE, 338);
2313 WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3);
2314 WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3);
2315 WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_WR_SIZE, 162);
2316 WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_RD_SIZE, 338);
2318 WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3);
2319 WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3);
2320 WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_WR_SIZE, 162);
2321 WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_RD_SIZE, 338);
2323 WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3);
2324 WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3);
2325 WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_WR_SIZE, 162);
2326 WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_RD_SIZE, 338);
2328 WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3);
2329 WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3);
2330 WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_WR_SIZE, 162);
2331 WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_RD_SIZE, 338);
2333 WREG32(mmSIF_RTR_CTRL_0_E2E_HBM_EN,
2335 WREG32(mmSIF_RTR_CTRL_0_E2E_PCI_EN,
2338 WREG32(mmSIF_RTR_CTRL_1_E2E_HBM_EN,
2340 WREG32(mmSIF_RTR_CTRL_1_E2E_PCI_EN,
2343 WREG32(mmSIF_RTR_CTRL_2_E2E_HBM_EN,
2345 WREG32(mmSIF_RTR_CTRL_2_E2E_PCI_EN,
2348 WREG32(mmSIF_RTR_CTRL_3_E2E_HBM_EN,
2350 WREG32(mmSIF_RTR_CTRL_3_E2E_PCI_EN,
2353 WREG32(mmSIF_RTR_CTRL_4_E2E_HBM_EN,
2355 WREG32(mmSIF_RTR_CTRL_4_E2E_PCI_EN,
2358 WREG32(mmSIF_RTR_CTRL_5_E2E_HBM_EN,
2360 WREG32(mmSIF_RTR_CTRL_5_E2E_PCI_EN,
2363 WREG32(mmSIF_RTR_CTRL_6_E2E_HBM_EN,
2365 WREG32(mmSIF_RTR_CTRL_6_E2E_PCI_EN,
2368 WREG32(mmSIF_RTR_CTRL_7_E2E_HBM_EN,
2370 WREG32(mmSIF_RTR_CTRL_7_E2E_PCI_EN,
2373 WREG32(mmNIF_RTR_CTRL_0_E2E_HBM_EN,
2375 WREG32(mmNIF_RTR_CTRL_0_E2E_PCI_EN,
2378 WREG32(mmNIF_RTR_CTRL_1_E2E_HBM_EN,
2380 WREG32(mmNIF_RTR_CTRL_1_E2E_PCI_EN,
2383 WREG32(mmNIF_RTR_CTRL_2_E2E_HBM_EN,
2385 WREG32(mmNIF_RTR_CTRL_2_E2E_PCI_EN,
2388 WREG32(mmNIF_RTR_CTRL_3_E2E_HBM_EN,
2390 WREG32(mmNIF_RTR_CTRL_3_E2E_PCI_EN,
2393 WREG32(mmNIF_RTR_CTRL_4_E2E_HBM_EN,
2395 WREG32(mmNIF_RTR_CTRL_4_E2E_PCI_EN,
2398 WREG32(mmNIF_RTR_CTRL_5_E2E_HBM_EN,
2400 WREG32(mmNIF_RTR_CTRL_5_E2E_PCI_EN,
2403 WREG32(mmNIF_RTR_CTRL_6_E2E_HBM_EN,
2405 WREG32(mmNIF_RTR_CTRL_6_E2E_PCI_EN,
2408 WREG32(mmNIF_RTR_CTRL_7_E2E_HBM_EN,
2410 WREG32(mmNIF_RTR_CTRL_7_E2E_PCI_EN,
2413 WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_EN,
2415 WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_EN,
2418 WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_EN,
2420 WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_EN,
2423 WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_EN,
2425 WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_EN,
2428 WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_EN,
2430 WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_EN,
2433 WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_EN,
2435 WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_EN,
2438 WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_EN,
2440 WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_EN,
2443 WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_EN,
2445 WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_EN,
2448 WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_EN,
2450 WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_EN,
2470 WREG32(mmDMA_IF_E_N_HBM0_WR_CRED_CNT, hbm0_wr);
2471 WREG32(mmDMA_IF_E_N_HBM1_WR_CRED_CNT, hbm1_wr);
2472 WREG32(mmDMA_IF_E_N_HBM0_RD_CRED_CNT, hbm0_rd);
2473 WREG32(mmDMA_IF_E_N_HBM1_RD_CRED_CNT, hbm1_rd);
2475 WREG32(mmDMA_IF_E_S_HBM0_WR_CRED_CNT, hbm0_wr);
2476 WREG32(mmDMA_IF_E_S_HBM1_WR_CRED_CNT, hbm1_wr);
2477 WREG32(mmDMA_IF_E_S_HBM0_RD_CRED_CNT, hbm0_rd);
2478 WREG32(mmDMA_IF_E_S_HBM1_RD_CRED_CNT, hbm1_rd);
2480 WREG32(mmDMA_IF_W_N_HBM0_WR_CRED_CNT, hbm0_wr);
2481 WREG32(mmDMA_IF_W_N_HBM1_WR_CRED_CNT, hbm1_wr);
2482 WREG32(mmDMA_IF_W_N_HBM0_RD_CRED_CNT, hbm0_rd);
2483 WREG32(mmDMA_IF_W_N_HBM1_RD_CRED_CNT, hbm1_rd);
2485 WREG32(mmDMA_IF_W_S_HBM0_WR_CRED_CNT, hbm0_wr);
2486 WREG32(mmDMA_IF_W_S_HBM1_WR_CRED_CNT, hbm1_wr);
2487 WREG32(mmDMA_IF_W_S_HBM0_RD_CRED_CNT, hbm0_rd);
2488 WREG32(mmDMA_IF_W_S_HBM1_RD_CRED_CNT, hbm1_rd);
2490 WREG32(mmDMA_IF_E_N_HBM_CRED_EN_0,
2493 WREG32(mmDMA_IF_E_S_HBM_CRED_EN_0,
2496 WREG32(mmDMA_IF_W_N_HBM_CRED_EN_0,
2499 WREG32(mmDMA_IF_W_S_HBM_CRED_EN_0,
2503 WREG32(mmDMA_IF_E_N_HBM_CRED_EN_1,
2506 WREG32(mmDMA_IF_E_S_HBM_CRED_EN_1,
2509 WREG32(mmDMA_IF_W_N_HBM_CRED_EN_1,
2512 WREG32(mmDMA_IF_W_S_HBM_CRED_EN_1,
2529 WREG32(mmTPC0_CFG_TPC_INTR_MASK + tpc_offset, 0x8FFE);
2539 WREG32(mmMME0_CTRL_EUS_ROLLUP_CNT_ADD, 3);
2540 WREG32(mmMME1_CTRL_EUS_ROLLUP_CNT_ADD, 3);
2541 WREG32(mmMME2_CTRL_EUS_ROLLUP_CNT_ADD, 3);
2542 WREG32(mmMME3_CTRL_EUS_ROLLUP_CNT_ADD, 3);
2576 WREG32(mmDMA0_QM_PQ_BASE_LO_0 + q_off, lower_32_bits(qman_pq_addr));
2577 WREG32(mmDMA0_QM_PQ_BASE_HI_0 + q_off, upper_32_bits(qman_pq_addr));
2579 WREG32(mmDMA0_QM_PQ_SIZE_0 + q_off, ilog2(HL_QUEUE_LENGTH));
2580 WREG32(mmDMA0_QM_PQ_PI_0 + q_off, 0);
2581 WREG32(mmDMA0_QM_PQ_CI_0 + q_off, 0);
2583 WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, QMAN_LDMA_SIZE_OFFSET);
2584 WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2586 WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2589 WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo);
2590 WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi);
2591 WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_en_lo);
2592 WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_en_hi);
2593 WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 + q_off, mtr_base_ws_lo);
2594 WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 + q_off, mtr_base_ws_hi);
2595 WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 + q_off, so_base_ws_lo);
2596 WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 + q_off, so_base_ws_hi);
2598 WREG32(mmDMA0_QM_CP_BARRIER_CFG_0 + q_off, 0x100);
2612 WREG32(mmDMA0_QM_GLBL_ERR_CFG + dma_qm_offset, dma_qm_err_cfg);
2614 WREG32(mmDMA0_QM_GLBL_ERR_ADDR_LO + dma_qm_offset,
2616 WREG32(mmDMA0_QM_GLBL_ERR_ADDR_HI + dma_qm_offset,
2619 WREG32(mmDMA0_QM_GLBL_ERR_WDATA + dma_qm_offset,
2623 WREG32(mmDMA0_QM_ARB_ERR_MSG_EN + dma_qm_offset,
2627 WREG32(mmDMA0_QM_ARB_SLV_CHOISE_WDT + dma_qm_offset, GAUDI_ARB_WDT_TIMEOUT);
2629 WREG32(mmDMA0_QM_GLBL_PROT + dma_qm_offset,
2632 WREG32(mmDMA0_QM_GLBL_CFG1 + dma_qm_offset, 0);
2645 WREG32(mmDMA0_CORE_RD_MAX_OUTSTAND + dma_offset, 0);
2646 WREG32(mmDMA0_CORE_RD_MAX_SIZE + dma_offset, 0);
2649 WREG32(mmDMA0_CORE_LBW_MAX_OUTSTAND + dma_offset, 15);
2655 WREG32(mmDMA0_CORE_ERR_CFG + dma_offset, dma_err_cfg);
2661 WREG32(mmDMA0_CORE_ERRMSG_ADDR_LO + dma_offset,
2663 WREG32(mmDMA0_CORE_ERRMSG_ADDR_HI + dma_offset,
2666 WREG32(mmDMA0_CORE_ERRMSG_WDATA + dma_offset,
2668 WREG32(mmDMA0_CORE_PROT + dma_offset,
2671 WREG32(mmDMA0_CORE_SECURE_PROPS + dma_offset,
2673 WREG32(mmDMA0_CORE_CFG_0 + dma_offset, 1 << DMA0_CORE_CFG_0_EN_SHIFT);
2681 WREG32(mmDMA0_QM_GLBL_CFG0 + dma_qm_offset, enable_mask);
2757 WREG32(mmDMA0_QM_PQ_BASE_LO_0 + q_off,
2759 WREG32(mmDMA0_QM_PQ_BASE_HI_0 + q_off,
2762 WREG32(mmDMA0_QM_PQ_SIZE_0 + q_off, ilog2(HBM_DMA_QMAN_LENGTH));
2763 WREG32(mmDMA0_QM_PQ_PI_0 + q_off, 0);
2764 WREG32(mmDMA0_QM_PQ_CI_0 + q_off, 0);
2766 WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
2768 WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2770 WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2777 WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
2779 WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2781 WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2790 WREG32(mmDMA0_QM_GLBL_ERR_CFG + dma_qm_offset, dma_qm_err_cfg);
2792 WREG32(mmDMA0_QM_GLBL_ERR_ADDR_LO + dma_qm_offset,
2794 WREG32(mmDMA0_QM_GLBL_ERR_ADDR_HI + dma_qm_offset,
2797 WREG32(mmDMA0_QM_GLBL_ERR_WDATA + dma_qm_offset,
2801 WREG32(mmDMA0_QM_ARB_ERR_MSG_EN + dma_qm_offset,
2805 WREG32(mmDMA0_QM_ARB_SLV_CHOISE_WDT + dma_qm_offset, GAUDI_ARB_WDT_TIMEOUT);
2807 WREG32(mmDMA0_QM_GLBL_CFG1 + dma_qm_offset, 0);
2808 WREG32(mmDMA0_QM_GLBL_PROT + dma_qm_offset,
2812 WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo);
2813 WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi);
2814 WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_en_lo);
2815 WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_en_hi);
2819 WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 + q_off,
2821 WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 + q_off,
2823 WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 + q_off,
2825 WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 + q_off,
2890 WREG32(mmMME0_QM_PQ_BASE_LO_0 + q_off,
2892 WREG32(mmMME0_QM_PQ_BASE_HI_0 + q_off,
2895 WREG32(mmMME0_QM_PQ_SIZE_0 + q_off, ilog2(MME_QMAN_LENGTH));
2896 WREG32(mmMME0_QM_PQ_PI_0 + q_off, 0);
2897 WREG32(mmMME0_QM_PQ_CI_0 + q_off, 0);
2899 WREG32(mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
2901 WREG32(mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2903 WREG32(mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2910 WREG32(mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
2912 WREG32(mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2914 WREG32(mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2926 WREG32(mmMME0_QM_GLBL_ERR_CFG + mme_offset, mme_qm_err_cfg);
2928 WREG32(mmMME0_QM_GLBL_ERR_ADDR_LO + mme_offset,
2930 WREG32(mmMME0_QM_GLBL_ERR_ADDR_HI + mme_offset,
2933 WREG32(mmMME0_QM_GLBL_ERR_WDATA + mme_offset,
2937 WREG32(mmMME0_QM_ARB_ERR_MSG_EN + mme_offset,
2941 WREG32(mmMME0_QM_ARB_SLV_CHOISE_WDT + mme_offset, GAUDI_ARB_WDT_TIMEOUT);
2943 WREG32(mmMME0_QM_GLBL_CFG1 + mme_offset, 0);
2944 WREG32(mmMME0_QM_GLBL_PROT + mme_offset,
2948 WREG32(mmMME0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_lo);
2949 WREG32(mmMME0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_hi);
2950 WREG32(mmMME0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_lo);
2951 WREG32(mmMME0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_hi);
2987 WREG32(mmMME2_QM_GLBL_CFG0, QMAN_MME_ENABLE);
2988 WREG32(mmMME0_QM_GLBL_CFG0, QMAN_MME_ENABLE);
3026 WREG32(mmTPC0_QM_PQ_BASE_LO_0 + q_off,
3028 WREG32(mmTPC0_QM_PQ_BASE_HI_0 + q_off,
3031 WREG32(mmTPC0_QM_PQ_SIZE_0 + q_off, ilog2(TPC_QMAN_LENGTH));
3032 WREG32(mmTPC0_QM_PQ_PI_0 + q_off, 0);
3033 WREG32(mmTPC0_QM_PQ_CI_0 + q_off, 0);
3035 WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
3037 WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
3039 WREG32(mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
3046 WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
3048 WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
3050 WREG32(mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
3059 WREG32(mmTPC0_QM_GLBL_ERR_CFG + tpc_offset, tpc_qm_err_cfg);
3061 WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + tpc_offset,
3063 WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + tpc_offset,
3066 WREG32(mmTPC0_QM_GLBL_ERR_WDATA + tpc_offset,
3070 WREG32(mmTPC0_QM_ARB_ERR_MSG_EN + tpc_offset,
3074 WREG32(mmTPC0_QM_ARB_SLV_CHOISE_WDT + tpc_offset, GAUDI_ARB_WDT_TIMEOUT);
3076 WREG32(mmTPC0_QM_GLBL_CFG1 + tpc_offset, 0);
3077 WREG32(mmTPC0_QM_GLBL_PROT + tpc_offset,
3081 WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo);
3082 WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi);
3083 WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_en_lo);
3084 WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_en_hi);
3088 WREG32(mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_0 + q_off,
3090 WREG32(mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_0 + q_off,
3092 WREG32(mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_0 + q_off,
3094 WREG32(mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_0 + q_off,
3129 WREG32(mmTPC0_QM_GLBL_CFG0 + tpc_offset,
3134 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + tpc_id * tpc_delta,
3173 WREG32(mmNIC0_QM0_PQ_BASE_LO_0 + q_off, lower_32_bits(qman_base_addr));
3174 WREG32(mmNIC0_QM0_PQ_BASE_HI_0 + q_off, upper_32_bits(qman_base_addr));
3176 WREG32(mmNIC0_QM0_PQ_SIZE_0 + q_off, ilog2(NIC_QMAN_LENGTH));
3177 WREG32(mmNIC0_QM0_PQ_PI_0 + q_off, 0);
3178 WREG32(mmNIC0_QM0_PQ_CI_0 + q_off, 0);
3180 WREG32(mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_0 + q_off,
3182 WREG32(mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
3184 WREG32(mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
3187 WREG32(mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo);
3188 WREG32(mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi);
3189 WREG32(mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_en_lo);
3190 WREG32(mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_en_hi);
3193 WREG32(mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0 + q_off, mtr_base_ws_lo);
3194 WREG32(mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0 + q_off, mtr_base_ws_hi);
3195 WREG32(mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0 + q_off, so_base_ws_lo);
3196 WREG32(mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0 + q_off, so_base_ws_hi);
3209 WREG32(mmNIC0_QM0_GLBL_ERR_CFG + nic_offset, nic_qm_err_cfg);
3211 WREG32(mmNIC0_QM0_GLBL_ERR_ADDR_LO + nic_offset,
3213 WREG32(mmNIC0_QM0_GLBL_ERR_ADDR_HI + nic_offset,
3216 WREG32(mmNIC0_QM0_GLBL_ERR_WDATA + nic_offset,
3220 WREG32(mmNIC0_QM0_ARB_ERR_MSG_EN + nic_offset,
3224 WREG32(mmNIC0_QM0_ARB_SLV_CHOISE_WDT + nic_offset, GAUDI_ARB_WDT_TIMEOUT);
3226 WREG32(mmNIC0_QM0_GLBL_CFG1 + nic_offset, 0);
3227 WREG32(mmNIC0_QM0_GLBL_PROT + nic_offset,
3272 WREG32(mmNIC0_QM0_GLBL_CFG0 + nic_offset, NIC_QMAN_ENABLE);
3291 WREG32(mmDMA0_QM_GLBL_CFG0, 0);
3292 WREG32(mmDMA1_QM_GLBL_CFG0, 0);
3293 WREG32(mmDMA5_QM_GLBL_CFG0, 0);
3303 WREG32(mmDMA2_QM_GLBL_CFG0, 0);
3304 WREG32(mmDMA3_QM_GLBL_CFG0, 0);
3305 WREG32(mmDMA4_QM_GLBL_CFG0, 0);
3306 WREG32(mmDMA6_QM_GLBL_CFG0, 0);
3307 WREG32(mmDMA7_QM_GLBL_CFG0, 0);
3317 WREG32(mmMME2_QM_GLBL_CFG0, 0);
3318 WREG32(mmMME0_QM_GLBL_CFG0, 0);
3331 WREG32(mmTPC0_QM_GLBL_CFG0 + tpc_offset, 0);
3350 WREG32(mmNIC0_QM0_GLBL_CFG0 + nic_offset, 0);
3368 WREG32(mmDMA0_QM_GLBL_CFG1, 0xF << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3369 WREG32(mmDMA1_QM_GLBL_CFG1, 0xF << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3370 WREG32(mmDMA5_QM_GLBL_CFG1, 0xF << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3382 WREG32(mmDMA2_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3383 WREG32(mmDMA3_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3384 WREG32(mmDMA4_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3385 WREG32(mmDMA6_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3386 WREG32(mmDMA7_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3397 WREG32(mmMME2_QM_GLBL_CFG1, 0x1F << MME0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3398 WREG32(mmMME0_QM_GLBL_CFG1, 0x1F << MME0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3408 WREG32(mmTPC0_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3409 WREG32(mmTPC1_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3410 WREG32(mmTPC2_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3411 WREG32(mmTPC3_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3412 WREG32(mmTPC4_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3413 WREG32(mmTPC5_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3414 WREG32(mmTPC6_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3415 WREG32(mmTPC7_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3425 WREG32(mmNIC0_QM0_GLBL_CFG1,
3431 WREG32(mmNIC0_QM1_GLBL_CFG1,
3437 WREG32(mmNIC1_QM0_GLBL_CFG1,
3443 WREG32(mmNIC1_QM1_GLBL_CFG1,
3449 WREG32(mmNIC2_QM0_GLBL_CFG1,
3455 WREG32(mmNIC2_QM1_GLBL_CFG1,
3461 WREG32(mmNIC3_QM0_GLBL_CFG1,
3467 WREG32(mmNIC3_QM1_GLBL_CFG1,
3473 WREG32(mmNIC4_QM0_GLBL_CFG1,
3479 WREG32(mmNIC4_QM1_GLBL_CFG1,
3492 WREG32(mmDMA0_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
3493 WREG32(mmDMA1_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
3494 WREG32(mmDMA5_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
3504 WREG32(mmDMA2_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
3505 WREG32(mmDMA3_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
3506 WREG32(mmDMA4_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
3507 WREG32(mmDMA6_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
3508 WREG32(mmDMA7_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
3519 WREG32(mmMME0_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
3520 WREG32(mmMME0_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
3521 WREG32(mmMME0_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
3522 WREG32(mmMME0_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
3523 WREG32(mmMME1_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
3524 WREG32(mmMME1_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
3525 WREG32(mmMME1_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
3526 WREG32(mmMME1_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
3527 WREG32(mmMME2_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
3528 WREG32(mmMME2_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
3529 WREG32(mmMME2_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
3530 WREG32(mmMME2_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
3531 WREG32(mmMME3_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
3532 WREG32(mmMME3_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
3533 WREG32(mmMME3_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
3534 WREG32(mmMME3_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
3544 WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
3545 WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
3546 WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
3547 WREG32(mmTPC3_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
3548 WREG32(mmTPC4_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
3549 WREG32(mmTPC5_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
3550 WREG32(mmTPC6_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
3551 WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
3563 WREG32(mmDMA0_QM_CGM_CFG + qman_offset, 0);
3564 WREG32(mmDMA0_QM_CGM_CFG1 + qman_offset, 0);
3569 WREG32(mmMME0_QM_CGM_CFG, 0);
3570 WREG32(mmMME0_QM_CGM_CFG1, 0);
3571 WREG32(mmMME2_QM_CGM_CFG, 0);
3572 WREG32(mmMME2_QM_CGM_CFG1, 0);
3575 WREG32(mmTPC0_QM_CGM_CFG + qman_offset, 0);
3576 WREG32(mmTPC0_QM_CGM_CFG1 + qman_offset, 0);
3585 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
3588 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0xC, 0);
3589 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0x8, 0);
3592 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 1);
3598 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
3663 WREG32(mmSTLB_CACHE_INV_BASE_39_8, prop->mmu_cache_mng_addr >> 8);
3664 WREG32(mmSTLB_CACHE_INV_BASE_49_40, prop->mmu_cache_mng_addr >> 40);
3667 WREG32(mmSTLB_MEM_CACHE_INVALIDATION, 1);
3673 WREG32(mmMMU_UP_MMU_ENABLE, 1);
3674 WREG32(mmMMU_UP_SPI_MASK, 0xF);
3676 WREG32(mmSTLB_HOP_CONFIGURATION, 0x30440);
3802 WREG32(mmCPU_IF_CPU_MSB_ADDR, hdev->cpu_pci_msb_addr);
3834 WREG32(mmCPU_IF_PQ_BASE_ADDR_LOW, lower_32_bits(cpu_pq->bus_address));
3835 WREG32(mmCPU_IF_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address));
3837 WREG32(mmCPU_IF_EQ_BASE_ADDR_LOW, lower_32_bits(eq->bus_address));
3838 WREG32(mmCPU_IF_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address));
3840 WREG32(mmCPU_IF_CQ_BASE_ADDR_LOW,
3842 WREG32(mmCPU_IF_CQ_BASE_ADDR_HIGH,
3845 WREG32(mmCPU_IF_PQ_LENGTH, HL_QUEUE_SIZE_IN_BYTES);
3846 WREG32(mmCPU_IF_EQ_LENGTH, HL_EQ_SIZE_IN_BYTES);
3847 WREG32(mmCPU_IF_CQ_LENGTH, HL_CPU_ACCESSIBLE_MEM_SIZE);
3850 WREG32(mmCPU_IF_EQ_RD_OFFS, 0);
3852 WREG32(mmCPU_IF_PF_PQ_PI, 0);
3854 WREG32(mmCPU_IF_QUEUE_INIT, PQ_INIT_STATUS_READY_FOR_CP_SINGLE_MSI);
3860 WREG32(irq_handler_offset,
3896 WREG32(mmPCIE_WRAP_LBW_PROT_OVR,
3912 WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY);
4039 WREG32(mmPCIE_AUX_FLR_CTRL, (PCIE_AUX_FLR_CTRL_HW_CTRL_MASK |
4051 WREG32(irq_handler_offset,
4083 WREG32(mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_H,
4089 WREG32(mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_L, CFG_RST_L_TPC_MASK);
4091 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H,
4101 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L,
4109 WREG32(mmPREBOOT_PCIE_EN, LKD_HARD_RESET_MAGIC);
4112 WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START, 1);
4114 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST,
4506 WREG32(db_reg_offset, db_value);
4516 WREG32(irq_handler_offset,
4571 WREG32(mmDMA0_CORE_SRC_BASE_LO + dma_offset,
4573 WREG32(mmDMA0_CORE_SRC_BASE_HI + dma_offset,
4575 WREG32(mmDMA0_CORE_DST_BASE_LO + dma_offset,
4577 WREG32(mmDMA0_CORE_DST_BASE_HI + dma_offset,
4579 WREG32(mmDMA0_CORE_DST_TSIZE_0 + dma_offset,
4581 WREG32(mmDMA0_CORE_COMMIT + dma_offset,
5559 WREG32(mmCPU_IF_EQ_RD_OFFS, val);
5603 WREG32(mmDMA0_CORE_ERR_CAUSE, err_cause);
5630 WREG32(mmDMA0_CORE_ERR_CAUSE, err_cause);
5791 WREG32(mmDMA0_CORE_WR_COMP_ADDR_LO + dma_offset,
5793 WREG32(mmDMA0_CORE_WR_COMP_ADDR_HI + dma_offset,
5795 WREG32(mmDMA0_CORE_WR_COMP_WDATA + dma_offset, 0x80000001);
5801 WREG32(mmDMA0_CORE_WR_AWUSER_31_11 + dma_offset,
5813 WREG32(mmDMA0_QM_ARB_CFG_0 + qman_offset, 0);
5818 WREG32(mmMME0_QM_ARB_CFG_0 + qman_offset, 0);
5823 WREG32(mmTPC0_QM_ARB_CFG_0 + qman_offset, 0);
5829 WREG32(mmNIC0_QM0_ARB_CFG_0 + qman_offset, 0);
5879 WREG32(mmDMA0_CORE_SRC_BASE_LO + dma_offset, lower_32_bits(addr));
5880 WREG32(mmDMA0_CORE_SRC_BASE_HI + dma_offset, upper_32_bits(addr));
5881 WREG32(mmDMA0_CORE_DST_BASE_LO + dma_offset, lower_32_bits(dma_addr));
5882 WREG32(mmDMA0_CORE_DST_BASE_HI + dma_offset, upper_32_bits(dma_addr));
5883 WREG32(mmDMA0_CORE_DST_TSIZE_0 + dma_offset, size_to_dma);
5884 WREG32(mmDMA0_CORE_COMMIT + dma_offset,
5909 WREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset, err_cause);
5963 WREG32(mmDMA0_QM_GLBL_CFG1 + qm_offset,
5978 WREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset, err_cause);
6012 WREG32(mmDMA0_QM_GLBL_CFG1 + qm_offset, cfg1);
6379 WREG32(mmDMA0_CORE_PROT + dma_offset,
6401 WREG32(mmDMA0_CORE_PROT + dma_offset, BIT(DMA0_CORE_PROT_ERR_VAL_SHIFT));
6646 WREG32(mmMMU_UP_RAZWI_WRITE_VLD, 0);
6654 WREG32(mmMMU_UP_RAZWI_READ_VLD, 0);
6676 WREG32(mmMMU_UP_PAGE_ERROR_CAPTURE, 0);
6687 WREG32(mmMMU_UP_ACCESS_ERROR_CAPTURE, 0);
6746 WREG32(params->block_address + GAUDI_ECC_MEM_SEL_OFFSET,
6761 WREG32(params->block_address + GAUDI_ECC_MEM_INFO_CLR_OFFSET, reg);
6977 WREG32(glbl_sts_addr + 4 * i, glbl_sts_clr_val);
7419 WREG32(base + (ch * 0x1000) + 0x06C, 0x1F1F);
7420 WREG32(base + (ch * 0x1000) + 0x07C, 0x1F1F);
7489 WREG32(mmTPC0_CFG_TPC_INTR_CAUSE + tpc_offset, 0);
7912 WREG32(mmSTLB_INV_PS, 3);
7913 WREG32(mmSTLB_CACHE_INV, gaudi->mmu_cache_inv_pi++);
7914 WREG32(mmSTLB_INV_PS, 2);
7924 WREG32(mmSTLB_INV_SET, 0);
7949 WREG32(MMU_ASID, asid);
7950 WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT);
7951 WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT);
7952 WREG32(MMU_BUSY, 0x80000000);
8203 WREG32(mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW + offset,
8205 WREG32(mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH + offset,
8208 WREG32(mmTPC0_CFG_ICACHE_BASE_ADDERESS_LOW + offset,
8210 WREG32(mmTPC0_CFG_ICACHE_BASE_ADDERESS_HIGH + offset,
8213 WREG32(mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_LO + offset,
8215 WREG32(mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_HI + offset,
8218 WREG32(mmTPC0_CFG_QM_SYNC_OBJECT_ADDR + offset,
8222 WREG32(mmTPC0_CFG_TPC_CMD + offset,
8245 WREG32(mmTPC0_CFG_TPC_EXECUTE + offset,
8752 WREG32(mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 +
8786 WREG32(irq_handler_offset,