Lines Matching refs:at1
63 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
77 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
82 rur.THREADPTR \at1 // threadptr option
83 s32i \at1, \ptr, .Lxchal_ofs_+0
92 rsr.ACCLO \at1 // MAC16 option
93 s32i \at1, \ptr, .Lxchal_ofs_+0
94 rsr.ACCHI \at1 // MAC16 option
95 s32i \at1, \ptr, .Lxchal_ofs_+4
104 rsr.M0 \at1 // MAC16 option
105 s32i \at1, \ptr, .Lxchal_ofs_+0
106 rsr.M1 \at1 // MAC16 option
107 s32i \at1, \ptr, .Lxchal_ofs_+4
108 rsr.M2 \at1 // MAC16 option
109 s32i \at1, \ptr, .Lxchal_ofs_+8
110 rsr.M3 \at1 // MAC16 option
111 s32i \at1, \ptr, .Lxchal_ofs_+12
112 rsr.BR \at1 // boolean option
113 s32i \at1, \ptr, .Lxchal_ofs_+16
114 rsr.SCOMPARE1 \at1 // conditional store option
115 s32i \at1, \ptr, .Lxchal_ofs_+20
129 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
143 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
148 l32i \at1, \ptr, .Lxchal_ofs_+0
149 wur.THREADPTR \at1 // threadptr option
158 l32i \at1, \ptr, .Lxchal_ofs_+0
159 wsr.ACCLO \at1 // MAC16 option
160 l32i \at1, \ptr, .Lxchal_ofs_+4
161 wsr.ACCHI \at1 // MAC16 option
170 l32i \at1, \ptr, .Lxchal_ofs_+0
171 wsr.M0 \at1 // MAC16 option
172 l32i \at1, \ptr, .Lxchal_ofs_+4
173 wsr.M1 \at1 // MAC16 option
174 l32i \at1, \ptr, .Lxchal_ofs_+8
175 wsr.M2 \at1 // MAC16 option
176 l32i \at1, \ptr, .Lxchal_ofs_+12
177 wsr.M3 \at1 // MAC16 option
178 l32i \at1, \ptr, .Lxchal_ofs_+16
179 wsr.BR \at1 // boolean option
180 l32i \at1, \ptr, .Lxchal_ofs_+20
181 wsr.SCOMPARE1 \at1 // conditional store option
200 * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
205 .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
210 rur.AE_OVF_SAR \at1 // ureg 240
211 s32i \at1, \ptr, .Lxchal_ofs_+0
212 rur.AE_BITHEAD \at1 // ureg 241
213 s32i \at1, \ptr, .Lxchal_ofs_+4
214 rur.AE_TS_FTS_BU_BP \at1 // ureg 242
215 s32i \at1, \ptr, .Lxchal_ofs_+8
216 rur.AE_CW_SD_NO \at1 // ureg 243
217 s32i \at1, \ptr, .Lxchal_ofs_+12
218 rur.AE_CBEGIN0 \at1 // ureg 246
219 s32i \at1, \ptr, .Lxchal_ofs_+16
220 rur.AE_CEND0 \at1 // ureg 247
221 s32i \at1, \ptr, .Lxchal_ofs_+20
257 * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
262 .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
267 l32i \at1, \ptr, .Lxchal_ofs_+0
268 wur.AE_OVF_SAR \at1 // ureg 240
269 l32i \at1, \ptr, .Lxchal_ofs_+4
270 wur.AE_BITHEAD \at1 // ureg 241
271 l32i \at1, \ptr, .Lxchal_ofs_+8
272 wur.AE_TS_FTS_BU_BP \at1 // ureg 242
273 l32i \at1, \ptr, .Lxchal_ofs_+12
274 wur.AE_CW_SD_NO \at1 // ureg 243
275 l32i \at1, \ptr, .Lxchal_ofs_+16
276 wur.AE_CBEGIN0 \at1 // ureg 246
277 l32i \at1, \ptr, .Lxchal_ofs_+20
278 wur.AE_CEND0 \at1 // ureg 247