Lines Matching refs:at1
62 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
76 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
81 rur.THREADPTR \at1 // threadptr option
82 s32i \at1, \ptr, .Lxchal_ofs_+0
91 rsr.ACCLO \at1 // MAC16 option
92 s32i \at1, \ptr, .Lxchal_ofs_+0
93 rsr.ACCHI \at1 // MAC16 option
94 s32i \at1, \ptr, .Lxchal_ofs_+4
103 rsr.BR \at1 // boolean option
104 s32i \at1, \ptr, .Lxchal_ofs_+0
105 rsr.SCOMPARE1 \at1 // conditional store option
106 s32i \at1, \ptr, .Lxchal_ofs_+4
107 rsr.M0 \at1 // MAC16 option
108 s32i \at1, \ptr, .Lxchal_ofs_+8
109 rsr.M1 \at1 // MAC16 option
110 s32i \at1, \ptr, .Lxchal_ofs_+12
111 rsr.M2 \at1 // MAC16 option
112 s32i \at1, \ptr, .Lxchal_ofs_+16
113 rsr.M3 \at1 // MAC16 option
114 s32i \at1, \ptr, .Lxchal_ofs_+20
128 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
142 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
147 l32i \at1, \ptr, .Lxchal_ofs_+0
148 wur.THREADPTR \at1 // threadptr option
157 l32i \at1, \ptr, .Lxchal_ofs_+0
158 wsr.ACCLO \at1 // MAC16 option
159 l32i \at1, \ptr, .Lxchal_ofs_+4
160 wsr.ACCHI \at1 // MAC16 option
169 l32i \at1, \ptr, .Lxchal_ofs_+0
170 wsr.BR \at1 // boolean option
171 l32i \at1, \ptr, .Lxchal_ofs_+4
172 wsr.SCOMPARE1 \at1 // conditional store option
173 l32i \at1, \ptr, .Lxchal_ofs_+8
174 wsr.M0 \at1 // MAC16 option
175 l32i \at1, \ptr, .Lxchal_ofs_+12
176 wsr.M1 \at1 // MAC16 option
177 l32i \at1, \ptr, .Lxchal_ofs_+16
178 wsr.M2 \at1 // MAC16 option
179 l32i \at1, \ptr, .Lxchal_ofs_+20
180 wsr.M3 \at1 // MAC16 option
196 * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
201 .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
206 rur.AE_OVF_SAR \at1 // ureg 240
207 s32i \at1, \ptr, .Lxchal_ofs_+0
208 rur.AE_BITHEAD \at1 // ureg 241
209 s32i \at1, \ptr, .Lxchal_ofs_+4
210 rur.AE_TS_FTS_BU_BP \at1 // ureg 242
211 s32i \at1, \ptr, .Lxchal_ofs_+8
212 rur.AE_SD_NO \at1 // ureg 243
213 s32i \at1, \ptr, .Lxchal_ofs_+12
214 rur.AE_CBEGIN0 \at1 // ureg 246
215 s32i \at1, \ptr, .Lxchal_ofs_+16
216 rur.AE_CEND0 \at1 // ureg 247
217 s32i \at1, \ptr, .Lxchal_ofs_+20
244 * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
249 .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
254 l32i \at1, \ptr, .Lxchal_ofs_+0
255 wur.AE_OVF_SAR \at1 // ureg 240
256 l32i \at1, \ptr, .Lxchal_ofs_+4
257 wur.AE_BITHEAD \at1 // ureg 241
258 l32i \at1, \ptr, .Lxchal_ofs_+8
259 wur.AE_TS_FTS_BU_BP \at1 // ureg 242
260 l32i \at1, \ptr, .Lxchal_ofs_+12
261 wur.AE_SD_NO \at1 // ureg 243
262 l32i \at1, \ptr, .Lxchal_ofs_+16
263 wur.AE_CBEGIN0 \at1 // ureg 246
264 l32i \at1, \ptr, .Lxchal_ofs_+20
265 wur.AE_CEND0 \at1 // ureg 247