Lines Matching refs:a4

174 	extui	a0, a4, INSN_OP0, 4	# get insn.op0 nibble
181 	bbsi.l	a4, OP1_SI_BIT + INSN_OP1, .Linvalid_instruction
209 	extui	a5, a4, INSN_OP1, 4
239 	extui	a5, a4, INSN_OP0, 4	# get insn.op0 nibble
247 	_bbci.l	a4, OP1_SI_BIT + INSN_OP1, .Lload
254 	extui	a6, a4, INSN_T, 4	# get source register
279 	extui	a5, a4, INSN_OP0, 4
287 	extui	a5, a4, INSN_OP1, 4
308 	extui	a4, a4, INSN_T, 4	# extract target register
310 	addx8	a4, a4, a5
311 	jx	a4			# jump to entry for target register
357 	movi	a4, 0
359 	s32i	a4, a3, EXC_TABLE_FIXUP
368 	l32i	a4, a2, PT_AREG4
383 	# a7: instruction pointer, a4: instruction, a3: value
390 	extui	a5, a4, INSN_OP0, 4	# extract OP0
399 	extui	a5, a4, INSN_OP1, 4	# extract OP1
410 	movi	a4, ~3
411 	and	a4, a4, a8		# align memory address
417 	addi	a4, a4, 8
424 	l32e	a5, a4, -8
426 	l32i	a5, a4, 0		# load lower address word
432 	s32e	a5, a4, -8
433 	l32e	a8, a4, -4
435 	s32i	a5, a4, 0		# store
436 	l32i	a8, a4, 4		# same for upper address word
442 	s32e	a6, a4, -4
444 	s32i	a6, a4, 4
450 	rsr	a4, lend		# check if we reached LEND
451 	bne	a7, a4, 1f
452 	rsr	a4, lcount		# and LCOUNT != 0
453 	beqz	a4, 1f
454 	addi	a4, a4, -1		# decrement LCOUNT and set
456 	wsr	a4, lcount
462 	rsr	a4, icountlevel
463 	beqz	a4, 1f
464 	bgeui	a4, LOCKLEVEL + 1, 1f
465 	rsr	a4, icount
466 	addi	a4, a4, 1
467 	wsr	a4, icount
469 	movi	a4, 0
471 	s32i	a4, a3, EXC_TABLE_FIXUP
480 	l32i	a4, a2, PT_AREG4
496 	s32i	a4, a2, PT_AREG4
502 	rsr	a4, depc
503 	s32i	a4, a2, PT_AREG2
509 	movi	a4, fast_unaligned_fixup
510 	s32i	a4, a3, EXC_TABLE_FIXUP
535 	l32i	a4, a3, 0	# load 2 words
539 	__src_b	a4, a4, a5	# a4 has the instruction
554 	l32i	a4, a2, PT_SAR
556 	wsr	a4, sar
558 	l32i	a4, a2, PT_AREG4