x86/pci/irq.c

53 	int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
54 	int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq,
56 	int (*lvl)(struct pci_dev *router, struct pci_dev *dev, int pirq,
341  * FinALi pirq rules are as follows:
350 			   int pirq)
359 	index = (pirq & 1) << 1 | (pirq & 8) >> 3;
369 			   int pirq, int irq)
381 	index = (pirq & 1) << 1 | (pirq & 8) >> 3;
391 			   int pirq, int irq)
393 	u8 mask = ~((pirq & 0xf0u) >> 4);
433  * ALI pirq entries are damn ugly, and completely undocumented.
434  * This has been figured out from pirq tables, and it's not a pretty
437 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
441 	WARN_ON_ONCE(pirq > 16);
442 	return irqmap[read_config_nybble(router, 0x48, pirq-1)];
445 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
450 	WARN_ON_ONCE(pirq > 16);
452 		write_config_nybble(router, 0x48, pirq-1, val);
490 static int pirq_esc_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
496 	reg = pirq;
508 static int pirq_esc_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
514 	reg = pirq;
527  * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
530 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
534 	pci_read_config_byte(router, pirq, &x);
538 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
540 	pci_write_config_byte(router, pirq, irq);
562 static int pirq_ib_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
567 	reg = pirq;
575 static int pirq_ib_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
580 	reg = pirq;
589  * The VIA pirq rules are nibble-based, like ALI,
593 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
595 	return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
598 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
600 	write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
605  * The VIA pirq rules are nibble-based, like ALI,
609 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
613 	WARN_ON_ONCE(pirq > 5);
614 	return read_config_nybble(router, 0x55, pirqmap[pirq-1]);
617 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
621 	WARN_ON_ONCE(pirq > 5);
622 	write_config_nybble(router, 0x55, pirqmap[pirq-1], irq);
627  * ITE 8330G pirq rules are nibble-based
631 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
635 	WARN_ON_ONCE(pirq > 4);
636 	return read_config_nybble(router, 0x43, pirqmap[pirq-1]);
639 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
643 	WARN_ON_ONCE(pirq > 4);
644 	write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
652 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
654 	return read_config_nybble(router, 0xb8, pirq >> 4);
657 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
659 	write_config_nybble(router, 0xb8, pirq >> 4, irq);
668 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
670 	return read_config_nybble(router, 0x5C, (pirq-1)^1);
673 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
675 	write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
724 			   int pirq)
729 	reg = pirq;
738 			   int pirq, int irq)
743 	reg = pirq;
820 			   int pirq)
825 	reg = pirq;
833 			   int pirq, int irq)
838 	reg = pirq;
857 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
859 	WARN_ON_ONCE(pirq >= 9);
860 	if (pirq > 8) {
861 		dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
864 	return read_config_nybble(router, 0x74, pirq-1);
867 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
869 	WARN_ON_ONCE(pirq >= 9);
870 	if (pirq > 8) {
871 		dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
874 	write_config_nybble(router, 0x74, pirq-1, irq);
889 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
891 	outb(pirq, 0xc00);
896 	int pirq, int irq)
898 	outb(pirq, 0xc00);
907  * The AMD756 pirq rules are nibble-based
911 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
915 	if (pirq <= 4)
916 		irq = read_config_nybble(router, 0x56, pirq - 1);
919 		 dev->vendor, dev->device, pirq, irq);
923 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
927 		 dev->vendor, dev->device, pirq, irq);
928 	if (pirq <= 4)
929 		write_config_nybble(router, 0x56, pirq - 1, irq);
936 static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
938 	outb(0x10 + ((pirq - 1) >> 1), 0x24);
939 	return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf);
942 static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
946 	outb(0x10 + ((pirq - 1) >> 1), 0x24);
948 	x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq));
955 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
1397 	int i, pirq, newirq;
1427 	pirq = info->irq[pin - 1].link;
1429 	if (!pirq) {
1434 		'A' + dpin - 1, pirq, mask, pirq_table->exclusive_irqs);
1440 	if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
1443 		r->set(pirq_router_dev, dev, pirq, 11);
1449 		pirq = 0x68;
1451 		dev->irq = r->get(pirq_router_dev, dev, pirq);
1479 	if ((pirq & 0xf0) == 0xf0) {
1480 		irq = pirq & 0xf;
1482 	} else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
1486 			r->lvl(pirq_router_dev, dev, pirq, irq);
1491 		if (r->set(pirq_router_dev, dev, pirq, newirq)) {
1493 				r->lvl(pirq_router_dev, dev, pirq, newirq);
1513 	/* Update IRQ for all devices with the same pirq value */
1523 		if (info->irq[pin - 1].link == pirq) {