x86/net/bpf_jit_comp32.c

324 	u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
341 			/* xor dreg_hi,dreg_hi */
342 			EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
346 			/* xor dreg_hi,dreg_hi */
347 			EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
358 		/* mov dword ptr [ebp+off],dreg_hi */
359 		EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
372 	u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
390 			/* xor dreg_hi,dreg_hi */
391 			EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
399 			/* xor dreg_hi,dreg_hi */
400 			EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
409 		EMIT1(add_1reg(0xC8, dreg_hi));
411 		/* mov ecx,dreg_hi */
412 		EMIT2(0x89, add_2reg(0xC0, IA32_ECX, dreg_hi));
413 		/* mov dreg_hi,dreg_lo */
414 		EMIT2(0x89, add_2reg(0xC0, dreg_hi, dreg_lo));
424 		/* mov dword ptr [ebp+off],dreg_hi */
425 		EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
703 	u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
714 	/* adc dreg_hi,0x0 */
715 	EMIT3(0x83, add_1reg(0xD0, dreg_hi), 0x00);
716 	/* neg dreg_hi */
717 	EMIT2(0xF7, add_1reg(0xD8, dreg_hi));
723 		/* mov dword ptr [ebp+off],dreg_hi */
724 		EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
737 	u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
754 	/* shld dreg_hi,dreg_lo,cl */
755 	EMIT3(0x0F, 0xA5, add_2reg(0xC0, dreg_hi, dreg_lo));
759 	/* if ecx >= 32, mov dreg_lo into dreg_hi and clear dreg_lo */
766 	/* mov dreg_hi,dreg_lo */
767 	EMIT2(0x89, add_2reg(0xC0, dreg_hi, dreg_lo));
775 		/* mov dword ptr [ebp+off],dreg_hi */
776 		EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
790 	u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
807 	/* shrd dreg_lo,dreg_hi,cl */
808 	EMIT3(0x0F, 0xAD, add_2reg(0xC0, dreg_lo, dreg_hi));
809 	/* sar dreg_hi,cl */
810 	EMIT2(0xD3, add_1reg(0xF8, dreg_hi));
812 	/* if ecx >= 32, mov dreg_hi to dreg_lo and set/clear dreg_hi depending on sign */
819 	/* mov dreg_lo,dreg_hi */
820 	EMIT2(0x89, add_2reg(0xC0, dreg_lo, dreg_hi));
821 	/* sar dreg_hi,31 */
822 	EMIT3(0xC1, add_1reg(0xF8, dreg_hi), 31);
828 		/* mov dword ptr [ebp+off],dreg_hi */
829 		EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
843 	u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
860 	/* shrd dreg_lo,dreg_hi,cl */
861 	EMIT3(0x0F, 0xAD, add_2reg(0xC0, dreg_lo, dreg_hi));
862 	/* shr dreg_hi,cl */
863 	EMIT2(0xD3, add_1reg(0xE8, dreg_hi));
865 	/* if ecx >= 32, mov dreg_hi to dreg_lo and clear dreg_hi */
872 	/* mov dreg_lo,dreg_hi */
873 	EMIT2(0x89, add_2reg(0xC0, dreg_lo, dreg_hi));
874 	/* xor dreg_hi,dreg_hi */
875 	EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
881 		/* mov dword ptr [ebp+off],dreg_hi */
882 		EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
896 	u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
906 		/* shld dreg_hi,dreg_lo,imm8 */
907 		EMIT4(0x0F, 0xA4, add_2reg(0xC0, dreg_hi, dreg_lo), val);
915 		/* mov dreg_hi,dreg_lo */
916 		EMIT2(0x89, add_2reg(0xC0, dreg_hi, dreg_lo));
922 		/* xor dreg_hi,dreg_hi */
923 		EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
930 		/* mov dword ptr [ebp+off],dreg_hi */
931 		EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
944 	u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
955 		/* shrd dreg_lo,dreg_hi,imm8 */
956 		EMIT4(0x0F, 0xAC, add_2reg(0xC0, dreg_lo, dreg_hi), val);
957 		/* shr dreg_hi,imm8 */
958 		EMIT3(0xC1, add_1reg(0xE8, dreg_hi), val);
962 		/* shr dreg_hi,imm8 */
963 		EMIT3(0xC1, add_1reg(0xE8, dreg_hi), value);
964 		/* mov dreg_lo,dreg_hi */
965 		EMIT2(0x89, add_2reg(0xC0, dreg_lo, dreg_hi));
966 		/* xor dreg_hi,dreg_hi */
967 		EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
971 		/* xor dreg_hi,dreg_hi */
972 		EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
979 		/* mov dword ptr [ebp+off],dreg_hi */
980 		EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
993 	u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
1003 		/* shrd dreg_lo,dreg_hi,imm8 */
1004 		EMIT4(0x0F, 0xAC, add_2reg(0xC0, dreg_lo, dreg_hi), val);
1005 		/* ashr dreg_hi,imm8 */
1006 		EMIT3(0xC1, add_1reg(0xF8, dreg_hi), val);
1010 		/* ashr dreg_hi,imm8 */
1011 		EMIT3(0xC1, add_1reg(0xF8, dreg_hi), value);
1012 		/* mov dreg_lo,dreg_hi */
1013 		EMIT2(0x89, add_2reg(0xC0, dreg_lo, dreg_hi));
1015 		/* ashr dreg_hi,imm8 */
1016 		EMIT3(0xC1, add_1reg(0xF8, dreg_hi), 31);
1018 		/* ashr dreg_hi,imm8 */
1019 		EMIT3(0xC1, add_1reg(0xF8, dreg_hi), 31);
1020 		/* mov dreg_lo,dreg_hi */
1021 		EMIT2(0x89, add_2reg(0xC0, dreg_lo, dreg_hi));
1028 		/* mov dword ptr [ebp+off],dreg_hi */
1029 		EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
2163 			u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
2188 				/* cmp dreg_hi,sreg_hi */
2189 				EMIT2(0x39, add_2reg(0xC0, dreg_hi, sreg_hi));
2201 			u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
2223 			/* cmp dreg_hi,sreg_hi */
2224 			EMIT2(0x39, add_2reg(0xC0, dreg_hi, sreg_hi));
2234 			u8 dreg_hi = IA32_EDX;
2250 					/* mov dreg_hi,dst_hi */
2252 					      add_2reg(0xC0, dreg_hi, dst_hi));
2267 				/* and dreg_hi,sreg_hi */
2268 				EMIT2(0x23, add_2reg(0xC0, sreg_hi, dreg_hi));
2269 				/* or dreg_lo,dreg_hi */
2270 				EMIT2(0x09, add_2reg(0xC0, dreg_lo, dreg_hi));
2278 			u8 dreg_hi = IA32_EDX;
2295 					/* mov dreg_hi,dst_hi */
2297 					      add_2reg(0xC0, dreg_hi, dst_hi));
2309 				/* and dreg_hi,sreg_hi */
2310 				EMIT2(0x23, add_2reg(0xC0, sreg_hi, dreg_hi));
2311 				/* or dreg_lo,dreg_hi */
2312 				EMIT2(0x09, add_2reg(0xC0, dreg_lo, dreg_hi));
2334 			u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
2355 				/* cmp dreg_hi,sreg_hi */
2356 				EMIT2(0x39, add_2reg(0xC0, dreg_hi, sreg_hi));
2381 			u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
2400 			/* cmp dreg_hi,sreg_hi */
2401 			EMIT2(0x39, add_2reg(0xC0, dreg_hi, sreg_hi));