3  * check TSC synchronization.
7  * We check whether all boot CPUs have their TSC's synchronized,
8  * print a warning if not and turn off the TSC clock-source.
25 #include <asm/tsc.h>
38  * TSC's on different sockets may be reset asynchronously.
39  * This may cause the TSC ADJUST value on socket 0 to be NOT 0.
48 	pr_info("tsc: Marking TSC async resets true due to %s\n", reason);  in mark_tsc_async_resets()
59 	/* Skip unnecessary error messages if TSC already unstable */  in tsc_verify_tsc_adjust()
77 		pr_warn(FW_BUG "TSC ADJUST differs: CPU%u %lld --> %lld. Restoring\n",  in tsc_verify_tsc_adjust()
135 	 * the TSC is in sync with the already running cpus.  in tsc_sanitize_first_cpu()
140 	 * and socket 0 may not have an TSC ADJUST value of 0.  in tsc_sanitize_first_cpu()
144 			pr_warn(FW_BUG "TSC ADJUST: CPU%u: %lld force to 0\n",  in tsc_sanitize_first_cpu()
149 			pr_info("TSC ADJUST: CPU%u: %lld NOT forced to 0\n",  in tsc_sanitize_first_cpu()
165 	/* Skip unnecessary error messages if TSC already unstable */  in tsc_store_and_check_tsc_adjust()
179  * Store and check the TSC ADJUST MSR if available
223 		printk_once(FW_BUG "TSC ADJUST differs within socket(s), fixing all errors\n");  in tsc_store_and_check_tsc_adjust()
253  * of a critical section, to be able to prove TSC time-warps:
263  * TSC-warp measurement loop running on both CPUs.  This is not called
264  * if there is no TSC.
279 		 * We take the global lock, measure TSC, save the  in check_tsc_warp()
280 		 * previous TSC that was measured (possibly on  in check_tsc_warp()
281 		 * another CPU) and update the previous TSC timestamp.  in check_tsc_warp()
293 		 * TSC readout is totally broken]):  in check_tsc_warp()
303 		 * we saw a time-warp of the TSC going backwards:  in check_tsc_warp()
321 		"Warning: zero tsc calibration delta: %Ld [max: %Ld]\n",  in check_tsc_warp()
328  * online, a timeout of 20msec will be used for the TSC-warp measurement
333  * Ideally we should be able to skip the TSC sync check on the other
335  * But as the TSC is per-logical CPU and can potentially be modified wrongly
336  * by the bios, TSC sync test for smaller duration should be able
392 		pr_debug("TSC synchronization [CPU#%d -> CPU#%u]: passed\n",  in check_tsc_sync_source()
399 		pr_warn("TSC synchronization [CPU#%d -> CPU#%u]:\n",  in check_tsc_sync_source()
401 		pr_warn("Measured %Ld cycles TSC warp between CPUs, "  in check_tsc_sync_source()
402 			"turning off TSC clock.\n", max_warp);  in check_tsc_sync_source()
404 			pr_warn("TSC warped randomly between CPUs\n");  in check_tsc_sync_source()
439 	/* Also aborts if there is no TSC. */  in check_tsc_sync_target()
444 	 * Store, verify and sanitize the TSC adjust register. If  in check_tsc_sync_target()
447 	 * The test is also skipped when the TSC is marked reliable. This  in check_tsc_sync_target()
449 	 * SoCs the TSC is frequency synchronized, but still the TSC ADJUST  in check_tsc_sync_target()
455 	/* Kick the control CPU into the TSC synchronization function */  in check_tsc_sync_target()
492 	 * failed and a retry with adjusted TSC is possible. If zero the  in check_tsc_sync_target()
500 	 * observed time going backwards so this TSC was ahead and  in check_tsc_sync_target()
510 	 * sync mechanism (observed values are ~200 TSC cycles), but this  in check_tsc_sync_target()
519 	pr_warn("TSC ADJUST compensate: CPU%u observed %lld warp. Adjust: %lld\n",  in check_tsc_sync_target()