Lines Matching +full:0 +full:x00800000
22 #define FPSCR_RCHG 0x00000000
46 asm volatile ("sts.l fpul, @-%0\n\t"
47 "sts.l fpscr, @-%0\n\t"
50 "fmov.s fr15, @-%0\n\t"
51 "fmov.s fr14, @-%0\n\t"
52 "fmov.s fr13, @-%0\n\t"
53 "fmov.s fr12, @-%0\n\t"
54 "fmov.s fr11, @-%0\n\t"
55 "fmov.s fr10, @-%0\n\t"
56 "fmov.s fr9, @-%0\n\t"
57 "fmov.s fr8, @-%0\n\t"
58 "fmov.s fr7, @-%0\n\t"
59 "fmov.s fr6, @-%0\n\t"
60 "fmov.s fr5, @-%0\n\t"
61 "fmov.s fr4, @-%0\n\t"
62 "fmov.s fr3, @-%0\n\t"
63 "fmov.s fr2, @-%0\n\t"
64 "fmov.s fr1, @-%0\n\t"
65 "fmov.s fr0, @-%0\n\t"
67 "fmov.s fr15, @-%0\n\t"
68 "fmov.s fr14, @-%0\n\t"
69 "fmov.s fr13, @-%0\n\t"
70 "fmov.s fr12, @-%0\n\t"
71 "fmov.s fr11, @-%0\n\t"
72 "fmov.s fr10, @-%0\n\t"
73 "fmov.s fr9, @-%0\n\t"
74 "fmov.s fr8, @-%0\n\t"
75 "fmov.s fr7, @-%0\n\t"
76 "fmov.s fr6, @-%0\n\t"
77 "fmov.s fr5, @-%0\n\t"
78 "fmov.s fr4, @-%0\n\t"
79 "fmov.s fr3, @-%0\n\t"
80 "fmov.s fr2, @-%0\n\t"
81 "fmov.s fr1, @-%0\n\t"
82 "fmov.s fr0, @-%0\n\t"
84 :"0"((char *)(&tsk->thread.xstate->hardfpu.status)),
97 "fmov.s @%0+, fr0\n\t"
98 "fmov.s @%0+, fr1\n\t"
99 "fmov.s @%0+, fr2\n\t"
100 "fmov.s @%0+, fr3\n\t"
101 "fmov.s @%0+, fr4\n\t"
102 "fmov.s @%0+, fr5\n\t"
103 "fmov.s @%0+, fr6\n\t"
104 "fmov.s @%0+, fr7\n\t"
105 "fmov.s @%0+, fr8\n\t"
106 "fmov.s @%0+, fr9\n\t"
107 "fmov.s @%0+, fr10\n\t"
108 "fmov.s @%0+, fr11\n\t"
109 "fmov.s @%0+, fr12\n\t"
110 "fmov.s @%0+, fr13\n\t"
111 "fmov.s @%0+, fr14\n\t"
112 "fmov.s @%0+, fr15\n\t"
114 "fmov.s @%0+, fr0\n\t"
115 "fmov.s @%0+, fr1\n\t"
116 "fmov.s @%0+, fr2\n\t"
117 "fmov.s @%0+, fr3\n\t"
118 "fmov.s @%0+, fr4\n\t"
119 "fmov.s @%0+, fr5\n\t"
120 "fmov.s @%0+, fr6\n\t"
121 "fmov.s @%0+, fr7\n\t"
122 "fmov.s @%0+, fr8\n\t"
123 "fmov.s @%0+, fr9\n\t"
124 "fmov.s @%0+, fr10\n\t"
125 "fmov.s @%0+, fr11\n\t"
126 "fmov.s @%0+, fr12\n\t"
127 "fmov.s @%0+, fr13\n\t"
128 "fmov.s @%0+, fr14\n\t"
129 "fmov.s @%0+, fr15\n\t"
131 "lds.l @%0+, fpscr\n\t"
132 "lds.l @%0+, fpul\n\t"
134 :"0" (tsk->thread.xstate), "r" (FPSCR_RCHG)
152 if (x != 0 && (x & 0x7f800000) == 0) {
153 du = (x & 0x80000000);
154 while ((x & 0x00800000) == 0) {
158 x &= 0x007fffff;
180 (insn >> 12) & 0xf,
181 (insn >> 8) & 0xf,
182 (insn >> 4) & 0xf,
183 insn & 0xf
186 if (nib[0] == 0xb || (nib[0] == 0x4 && nib[2] == 0x0 && nib[3] == 0xb))
189 if (nib[0] == 0xa || nib[0] == 0xb) {
191 nextpc = regs->pc + 4 + ((short)((insn & 0xfff) << 4) >> 3);
193 } else if (nib[0] == 0x8 && nib[1] == 0xd) {
196 nextpc = regs->pc + 4 + ((char)(insn & 0xff) << 1);
200 } else if (nib[0] == 0x8 && nib[1] == 0xf) {
205 nextpc = regs->pc + 4 + ((char)(insn & 0xff) << 1);
207 } else if (nib[0] == 0x4 && nib[3] == 0xb &&
208 (nib[2] == 0x0 || nib[2] == 0x2)) {
212 } else if (nib[0] == 0x0 && nib[3] == 0x3 &&
213 (nib[2] == 0x0 || nib[2] == 0x2)) {
217 } else if (insn == 0x000b) {
226 if ((finsn & 0xf1ff) == 0xf0ad) {
233 (finsn >> 8) & 0xf);
235 return 0;
239 } else if ((finsn & 0xf00f) == 0xf002) {
246 n = (finsn >> 8) & 0xf;
247 m = (finsn >> 4) & 0xf;
254 && (prec && ((hx & 0x7fffffff) < 0x00100000
255 || (hy & 0x7fffffff) < 0x00100000))) {
265 tsk->thread.xstate->hardfpu.fp_regs[n + 1] = llx & 0xffffffff;
267 && (!prec && ((hx & 0x7fffffff) < 0x00800000
268 || (hy & 0x7fffffff) < 0x00800000))) {
273 return 0;
277 } else if ((finsn & 0xf00e) == 0xf000) {
284 n = (finsn >> 8) & 0xf;
285 m = (finsn >> 4) & 0xf;
292 && (prec && ((hx & 0x7fffffff) < 0x00100000
293 || (hy & 0x7fffffff) < 0x00100000))) {
301 if ((finsn & 0xf00f) == 0xf000)
306 tsk->thread.xstate->hardfpu.fp_regs[n + 1] = llx & 0xffffffff;
308 && (!prec && ((hx & 0x7fffffff) < 0x00800000
309 || (hy & 0x7fffffff) < 0x00800000))) {
311 if ((finsn & 0xf00f) == 0xf000)
317 return 0;
321 } else if ((finsn & 0xf003) == 0xf003) {
328 n = (finsn >> 8) & 0xf;
329 m = (finsn >> 4) & 0xf;
336 && (prec && ((hx & 0x7fffffff) < 0x00100000
337 || (hy & 0x7fffffff) < 0x00100000))) {
349 tsk->thread.xstate->hardfpu.fp_regs[n + 1] = llx & 0xffffffff;
351 && (!prec && ((hx & 0x7fffffff) < 0x00800000
352 || (hy & 0x7fffffff) < 0x00800000))) {
357 return 0;
361 } else if ((finsn & 0xf0bd) == 0xf0bd) {
367 m = (finsn >> 8) & 0x7;
371 && ((hx & 0x7fffffff) < 0x00100000)) {
380 return 0;
386 return 0;
407 fpu_exception_flags = 0;
419 (fpu_exception_flags >> 2)) == 0) {