Lines Matching +full:0 +full:x42000000
20 reg = <0x00000000 0x80000000 0x00000010 0x00000000>;
26 #clock-cells = <0>;
37 reg = <0x6c 0x00000000 0x0 0x00001000>,
38 <0x6c 0x00300000 0x0 0x00004000>,
39 <0x48 0x00000000 0x0 0x00001000>,
40 <0x6c 0x000c0000 0x0 0x00001000>;
48 interrupt-map-mask = <0 0 0 7>;
49 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
50 <0 0 0 2 &pcie_intc0 1>,
51 <0 0 0 3 &pcie_intc0 2>,
52 <0 0 0 4 &pcie_intc0 3>;
54 ranges = <0x01000000 0x0 0x00000000 0x48 0x10000000 0x0 0x00200000>,
55 <0x42000000 0x0 0x10000000 0x0 0x10000000 0x0 0x04000000>,
56 <0x02000000 0x0 0x14000000 0x0 0x14000000 0x0 0x04000000>,
57 <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>,
58 <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>;
62 #address-cells = <0>;
72 reg = <0x6c 0x00400000 0x0 0x00001000>,
73 <0x6c 0x00700000 0x0 0x00004000>,
74 <0x40 0x00000000 0x0 0x00001000>,
75 <0x6c 0x00780000 0x0 0x00001000>;
83 interrupt-map-mask = <0 0 0 7>;
84 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
85 <0 0 0 2 &pcie_intc1 1>,
86 <0 0 0 3 &pcie_intc1 2>,
87 <0 0 0 4 &pcie_intc1 3>;
89 ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00200000>,
90 <0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x04000000>,
91 <0x02000000 0x0 0x04000000 0x0 0x04000000 0x0 0x04000000>,
92 <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
93 <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
97 #address-cells = <0>;
107 reg = <0x6c 0x04000000 0x0 0x00001000>,
108 <0x6c 0x04300000 0x0 0x00004000>,
109 <0x58 0x00000000 0x0 0x00001000>,
110 <0x6c 0x040c0000 0x0 0x00001000>;
118 interrupt-map-mask = <0 0 0 7>;
119 interrupt-map = <0 0 0 1 &pcie_intc2 0>,
120 <0 0 0 2 &pcie_intc2 1>,
121 <0 0 0 3 &pcie_intc2 2>,
122 <0 0 0 4 &pcie_intc2 3>;
124 ranges = <0x01000000 0x0 0x00000000 0x58 0x10000000 0x0 0x00200000>,
125 <0x42000000 0x0 0x30000000 0x0 0x30000000 0x0 0x04000000>,
126 <0x02000000 0x0 0x34000000 0x0 0x34000000 0x0 0x04000000>,
127 <0x43000000 0x5a 0x00000000 0x5a 0x00000000 0x2 0x00000000>,
128 <0x03000000 0x59 0x00000000 0x59 0x00000000 0x1 0x00000000>;
132 #address-cells = <0>;
142 reg = <0x6c 0x04400000 0x0 0x00001000>,
143 <0x6c 0x04700000 0x0 0x00004000>,
144 <0x50 0x00000000 0x0 0x00001000>,
145 <0x6c 0x04780000 0x0 0x00001000>;
153 interrupt-map-mask = <0 0 0 7>;
154 interrupt-map = <0 0 0 1 &pcie_intc3 0>,
155 <0 0 0 2 &pcie_intc3 1>,
156 <0 0 0 3 &pcie_intc3 2>,
157 <0 0 0 4 &pcie_intc3 3>;
159 ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>,
160 <0x42000000 0x0 0x20000000 0x0 0x20000000 0x0 0x04000000>,
161 <0x02000000 0x0 0x24000000 0x0 0x24000000 0x0 0x04000000>,
162 <0x43000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>,
163 <0x03000000 0x51 0x00000000 0x51 0x00000000 0x1 0x00000000>;
167 #address-cells = <0>;
177 reg = <0x6c 0x08400000 0x0 0x00001000>,
178 <0x6c 0x08700000 0x0 0x00004000>,
179 <0x60 0x00000000 0x0 0x00001000>,
180 <0x6c 0x08780000 0x0 0x00001000>;
188 interrupt-map-mask = <0 0 0 7>;
189 interrupt-map = <0 0 0 1 &pcie_intc4 0>,
190 <0 0 0 2 &pcie_intc4 1>,
191 <0 0 0 3 &pcie_intc4 2>,
192 <0 0 0 4 &pcie_intc4 3>;
194 ranges = <0x01000000 0x0 0x00000000 0x60 0x10000000 0x0 0x00200000>,
195 <0x42000000 0x0 0x40000000 0x0 0x40000000 0x0 0x04000000>,
196 <0x02000000 0x0 0x44000000 0x0 0x44000000 0x0 0x04000000>,
197 <0x43000000 0x62 0x00000000 0x62 0x00000000 0x2 0x00000000>,
198 <0x03000000 0x61 0x00000000 0x61 0x00000000 0x1 0x00000000>;
202 #address-cells = <0>;
212 reg = <0x6d 0x50000000 0x0 0x800>,
213 <0x0 0x7ee00000 0x0 0x40>;
215 #msi-cells = <0>;
223 reg = <0x70 0x01000000 0x0 0x4000000>;
225 #size-cells = <0>;
235 reg = <0x70 0x05000000 0x0 0x4000000>;
237 #size-cells = <0>;
247 reg = <0x70 0x20000000 0x0 0x10000>;
256 snps,priority = <0 1 2 3 4 5 6 7>;
267 reg = <0x70 0x30000000 0x0 0x1000>;
282 reg = <0x70 0x30001000 0x0 0x1000>;
297 reg = <0x70 0x30002000 0x0 0x1000>;
312 reg = <0x70 0x30003000 0x0 0x1000>;
327 reg = <0x70 0x30006000 0x0 0x4000>;
338 snps,multicast-filter-bins = <0>;
352 #size-cells = <0>;
381 snps,blen = <16 8 4 0 0 0 0>;
389 reg = <0x70 0x3000a000 0x0 0x1000>;
401 reg = <0x70 0x3000b000 0x0 0x1000>;
413 reg = <0x70 0x40005000 0x0 0x1000>;
415 #size-cells = <0>;
427 reg = <0x70 0x40006000 0x0 0x1000>;
429 #size-cells = <0>;
441 reg = <0x70 0x40007000 0x0 0x1000>;
443 #size-cells = <0>;
455 reg = <0x70 0x40008000 0x0 0x1000>;
457 #size-cells = <0>;
469 reg = <0x70 0x40009000 0x0 0x1000>;
471 #size-cells = <0>;
477 porta: gpio-controller@0 {
479 reg = <0>;
492 reg = <0x70 0x4000a000 0x0 0x1000>;
494 #size-cells = <0>;
500 portb: gpio-controller@0 {
502 reg = <0>;
515 reg = <0x70 0x4000b000 0x0 0x1000>;
517 #size-cells = <0>;
523 portc: gpio-controller@0 {
525 reg = <0>;
538 reg = <0x70 0x4000c000 0x0 0x1000>;
548 reg = <0x70 0x50000000 0x0 0x1000>;
555 reg = <0x70 0x50001000 0x0 0x1000>;
560 reg = <0x70 0x50002000 0x0 0x1000>;
581 reg = <0x70 0x50003000 0x0 0x1000>;