platforms/52xx/mpc52xx_pci.c

111 	struct pci_controller *hose = pci_bus_to_host(bus);
115 		if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
118 	out_be32(hose->cfg_addr,
131 			value = in_8(((u8 __iomem *)hose->cfg_data) +
135 			value = in_le16(((u16 __iomem *)hose->cfg_data) +
140 			value = in_le16((u16 __iomem *)hose->cfg_data) |
141 				(in_le16(((u16 __iomem *)hose->cfg_data) + 1) << 16);
148 		value = in_le32(hose->cfg_data);
158 	out_be32(hose->cfg_addr, 0);
168 	struct pci_controller *hose = pci_bus_to_host(bus);
172 		if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
175 	out_be32(hose->cfg_addr,
188 			out_8(((u8 __iomem *)hose->cfg_data) +
192 			out_le16(((u16 __iomem *)hose->cfg_data) +
197 			out_le16((u16 __iomem *)hose->cfg_data,
199 			out_le16(((u16 __iomem *)hose->cfg_data) + 1,
208 			value = in_le32(hose->cfg_data);
218 		out_le32(hose->cfg_data, val);
222 	out_be32(hose->cfg_addr, 0);
239 mpc52xx_pci_setup(struct pci_controller *hose,
246 	pr_debug("%s(hose=%p, pci_regs=%p)\n", __func__, hose, pci_regs);
250 	hose->cfg_addr = &pci_regs->car;
251 	hose->cfg_data = hose->io_base_virt;
259 	res = &hose->mem_resources[0];
272 	res = &hose->mem_resources[1];
286 	res = &hose->io_resource;
292 		 res, &hose->io_base_phys);
294 	         MPC52xx_PCI_IWBTAR_TRANSLATION(hose->io_base_phys,
359 	struct pci_controller *hose;
387 	hose = pcibios_alloc_controller(node);
388 	if (!hose)
391 	hose->first_busno = bus_range ? bus_range[0] : 0;
392 	hose->last_busno = bus_range ? bus_range[1] : 0xff;
394 	hose->ops = &mpc52xx_pci_ops;
400 	pci_process_bridge_OF_ranges(hose, node, 1);
404 	mpc52xx_pci_setup(hose, pci_regs, rsrc.start);