platforms/44x/pci.c

1229 	void __iomem *mbase;
1234 	mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
1235 	if (mbase == NULL) {
1241 	while (attempt && (0 == (in_le32(mbase + PECFG_460SX_DLLSTA)
1248 	iounmap(mbase);
1271 	void __iomem *mbase = ioremap(port->cfg_space.start + 0x10000000,
1276 	if (mbase == NULL) {
1283 		val = in_le32(mbase + PECFG_TLDLP);
1296 	iounmap(mbase);
1603 					     void __iomem		*mbase,
1630 		out_le32(mbase + PECFG_POM0LAH, pciah);
1631 		out_le32(mbase + PECFG_POM0LAL, pcial);
1653 		out_le32(mbase + PECFG_POM1LAH, pciah);
1654 		out_le32(mbase + PECFG_POM1LAL, pcial);
1662 		out_le32(mbase + PECFG_POM2LAH, pciah);
1663 		out_le32(mbase + PECFG_POM2LAL, pcial);
1679 					       void __iomem *mbase)
1698 		if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1716 		if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1726 		ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1733 					       void __iomem *mbase,
1752 		out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1753 		out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa) |
1757 		out_le32(mbase + PECFG_BAR1MPA, 0);
1758 		out_le32(mbase + PECFG_BAR2HMPA, 0);
1759 		out_le32(mbase + PECFG_BAR2LMPA, 0);
1761 		out_le32(mbase + PECFG_PIM01SAH, RES_TO_U32_HIGH(sa));
1762 		out_le32(mbase + PECFG_PIM01SAL, RES_TO_U32_LOW(sa));
1764 		out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(ep_addr));
1765 		out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(ep_addr));
1779 		out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1780 		out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa));
1785 		out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
1786 		out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
1787 		out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
1788 		out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
1789 		out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
1790 		out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
1792 		out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start));
1793 		out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start));
1797 	out_le32(mbase + PECFG_PIMEN, 0x1);
1800 	out_le16(mbase + PCI_COMMAND,
1801 		 in_le16(mbase + PCI_COMMAND) |
1811 	void __iomem *mbase = NULL, *cfg_data = NULL;
1864 	mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
1865 	if (mbase == NULL) {
1870 	hose->cfg_addr = mbase;
1880 	mbase = (void __iomem *)hose->cfg_addr;
1886 		out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno);
1887 		out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1);
1888 		out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno);
1894 	out_le32(mbase + PECFG_PIMEN, 0);
1900 	if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0)
1904 	ppc4xx_configure_pciex_POMs(port, hose, mbase);
1907 	ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window);
1926 	out_le16(mbase + 0x200, val);
1937 	out_le16(mbase + 0x202, val);
1941 		out_le16(mbase + 0x204, 0x7);
1945 		out_le32(mbase + 0x208, 0x06040001);
1951 		out_le32(mbase + 0x208, 0x0b200001);
1963 	if (mbase)
1964 		iounmap(mbase);