Lines Matching +full:bus +full:- +full:range
1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * Common pmac/prep/chrp pci routines. -- Cort
37 #include <asm/pci-bridge.h>
40 #include <asm/ppc-pci.h>
73 int ret, phb_id = -1;
78 * the respective device-tree properties. Firstly, try reading
79 * standard "linux,pci-domain", then try reading "ibm,opal-phbid"
80 * (only present in powernv OPAL environment), then try device-tree
89 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop);
105 phb_id = (int)(prop & (MAX_PHBS - 1));
132 phb->global_number = get_phb_number(dev);
135 list_add_tail(&phb->list_node, &hose_list);
138 phb->dn = of_node_get(dev);
139 phb->is_dynamic = slab_is_available();
159 if (phb->global_number < MAX_PHBS)
160 clear_bit(phb->global_number, phb_bitmap);
161 of_node_put(phb->dn);
162 list_del(&phb->list_node);
165 if (phb->is_dynamic)
177 * The callback occurs when all references to the root bus
181 * which is associated with the 'struct pci_controller.bus'
182 * (root bus) - it expects .release_data to hold a pointer
198 bridge->release_data;
200 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic);
212 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
215 struct pci_controller *phb = pci_bus_to_host(bus);
217 if (phb->controller_ops.window_alignment)
218 return phb->controller_ops.window_alignment(bus, type);
228 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
230 struct pci_controller *hose = pci_bus_to_host(bus);
232 if (hose->controller_ops.setup_bridge)
233 hose->controller_ops.setup_bridge(bus, type);
238 struct pci_controller *phb = pci_bus_to_host(dev->bus);
240 if (phb->controller_ops.reset_secondary_bus) {
241 phb->controller_ops.reset_secondary_bus(dev);
286 return hose->pci_io_size;
288 return resource_size(&hose->io_resource);
301 if (address >= hose->io_base_virt &&
302 address < (hose->io_base_virt + size)) {
320 if (address >= hose->io_base_phys &&
321 address < (hose->io_base_phys + size)) {
323 (unsigned long)hose->io_base_virt - _IO_BASE;
324 ret = base + (address - hose->io_base_phys);
335 * Return the domain number for this bus.
337 int pci_domain_nr(struct pci_bus *bus)
339 struct pci_controller *hose = pci_bus_to_host(bus);
341 return hose->global_number;
346 * PCI bus numbers have not yet been assigned, and you need to
357 if (hose->dn == node)
359 node = node->parent;
369 if (hose->global_number == domain_nr)
388 list_del(&vi->list_node);
389 irq_dispose_mapping(vi->virq);
403 if (vi->virq == pdev->irq) {
404 kref_put(&vi->kref, ppc_pci_intx_release);
437 return -1;
441 /* Try to get a mapping from the device-tree */
476 pci_dev->irq = virq;
480 if (vitmp->virq == virq) {
481 kref_get(&vitmp->kref);
488 vi->virq = virq;
489 kref_init(&vi->kref);
490 list_add_tail(&vi->list_node, &intx_list);
497 return -1;
501 * Platform support for /proc/bus/pci/X/Y mmap()s.
502 * -- paulus.
506 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
510 return -EINVAL;
513 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
515 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
539 struct resource *rp = &pdev->resource[i];
540 int flags = rp->flags;
545 /* In the range of this resource? */
546 if (offset < (rp->start & PAGE_MASK) ||
547 offset > rp->end)
556 if (found->flags & IORESOURCE_PREFETCH)
561 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
567 /* This provides legacy IO read access on a bus */
568 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
571 struct pci_controller *hose = pci_bus_to_host(bus);
572 struct resource *rp = &hose->io_resource;
575 /* Check if port can be supported by that bus. We only check
576 * the ranges of the PHB though, not the bus itself as the rules
580 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
583 if (!(rp->flags & IORESOURCE_IO))
584 return -ENXIO;
585 if (offset < rp->start || (offset + size) > rp->end)
586 return -ENXIO;
587 addr = hose->io_base_virt + port;
595 return -EINVAL;
600 return -EINVAL;
604 return -EINVAL;
607 /* This provides legacy IO write access on a bus */
608 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
611 struct pci_controller *hose = pci_bus_to_host(bus);
612 struct resource *rp = &hose->io_resource;
615 /* Check if port can be supported by that bus. We only check
616 * the ranges of the PHB though, not the bus itself as the rules
620 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
623 if (!(rp->flags & IORESOURCE_IO))
624 return -ENXIO;
625 if (offset < rp->start || (offset + size) > rp->end)
626 return -ENXIO;
627 addr = hose->io_base_virt + port;
640 return -EINVAL;
645 return -EINVAL;
649 return -EINVAL;
652 /* This provides legacy IO or memory mmap access on a bus */
653 int pci_mmap_legacy_page_range(struct pci_bus *bus,
657 struct pci_controller *hose = pci_bus_to_host(bus);
659 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
660 resource_size_t size = vma->vm_end - vma->vm_start;
664 pci_domain_nr(bus), bus->number,
667 (unsigned long long)(offset + size - 1));
677 if ((offset + size) > hose->isa_mem_size) {
679 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
680 current->comm, current->pid, pci_domain_nr(bus), bus->number);
681 if (vma->vm_flags & VM_SHARED)
685 offset += hose->isa_mem_phys;
687 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
689 rp = &hose->io_resource;
690 if (!(rp->flags & IORESOURCE_IO))
691 return -ENXIO;
692 if (roffset < rp->start || (roffset + size) > rp->end)
693 return -ENXIO;
694 offset += hose->io_base_phys;
696 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
698 vma->vm_pgoff = offset >> PAGE_SHIFT;
699 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
700 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
701 vma->vm_end - vma->vm_start,
702 vma->vm_page_prot);
711 if (rsrc->flags & IORESOURCE_IO) {
712 pcibios_resource_to_bus(dev->bus, ®ion,
723 * That means we may have 64-bit values where some apps only expect
724 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
726 *start = rsrc->start;
727 *end = rsrc->end;
731 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
734 * @primary: set if primary bus (32 bits only, soon to be deprecated)
743 * - We can only cope with one IO space range and up to 3 Memory space
747 * - Some busses have IO space not starting at 0, which causes trouble with
751 * - Some 32 bits platforms such as 4xx can have physical space larger than
759 struct of_pci_range range;
770 for_each_of_pci_range(&parser, &range) {
771 /* If we failed translation or got a zero-sized region
776 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
781 switch (range.flags & IORESOURCE_TYPE_BITS) {
784 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
785 range.cpu_addr, range.cpu_addr + range.size - 1,
786 range.pci_addr);
788 /* We support only one IO range */
789 if (hose->pci_io_size) {
791 " \\--> Skipped (too many) !\n");
796 if (range.size > 0x01000000)
797 range.size = 0x01000000;
800 hose->io_base_virt = ioremap(range.cpu_addr,
801 range.size);
806 (unsigned long)hose->io_base_virt;
811 hose->pci_io_size = range.pci_addr + range.size;
812 hose->io_base_phys = range.cpu_addr - range.pci_addr;
815 res = &hose->io_resource;
816 range.cpu_addr = range.pci_addr;
820 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
821 range.cpu_addr, range.cpu_addr + range.size - 1,
822 range.pci_addr,
823 (range.flags & IORESOURCE_PREFETCH) ?
829 " \\--> Skipped (too many) !\n");
833 if (range.pci_addr == 0) {
835 isa_mem_base = range.cpu_addr;
836 hose->isa_mem_phys = range.cpu_addr;
837 hose->isa_mem_size = range.size;
841 hose->mem_offset[memno] = range.cpu_addr -
842 range.pci_addr;
843 res = &hose->mem_resources[memno++];
847 res->name = dev->full_name;
848 res->flags = range.flags;
849 res->start = range.cpu_addr;
850 res->end = range.cpu_addr + range.size - 1;
851 res->parent = res->child = res->sibling = NULL;
857 int pci_proc_domain(struct pci_bus *bus)
859 struct pci_controller *hose = pci_bus_to_host(bus);
864 return hose->global_number != 0;
881 struct pci_controller *hose = pci_bus_to_host(dev->bus);
891 if (dev->is_virtfn)
897 if (!res->flags)
900 /* If we're going to re-assign everything, we mark all resources
901 * as unset (and 0-base them). In addition, we mark BARs starting
903 * since in that case, we don't want to re-assign anything
905 pcibios_resource_to_bus(dev->bus, ®, res);
908 /* Only print message if not re-assigning */
912 res->end -= res->start;
913 res->start = 0;
914 res->flags |= IORESOURCE_UNSET;
930 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
932 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
935 struct pci_controller *hose = pci_bus_to_host(bus);
936 struct pci_dev *dev = bus->self;
947 if (res->flags & IORESOURCE_MEM) {
948 pcibios_resource_to_bus(dev->bus, ®ion, res);
950 /* If the BAR is non-0 then it's probably been initialized */
966 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
967 hose->mem_resources[i].start == hose->mem_offset[i])
976 /* If the BAR is non-0, then we consider it assigned */
977 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
978 if (((res->start - offset) & 0xfffffffful) != 0)
982 * starting at low addresses -is- valid. What we do instead if that
997 /* Fixup resources of a PCI<->PCI bridge */
998 static void pcibios_fixup_bridge(struct pci_bus *bus)
1003 struct pci_dev *dev = bus->self;
1005 pci_bus_for_each_resource(bus, res, i) {
1006 if (!res || !res->flags)
1008 if (i >= 3 && bus->self->transparent)
1016 res->flags |= IORESOURCE_UNSET;
1017 res->start = 0;
1018 res->end = -1;
1022 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
1025 * and clear them out so they get re-assigned later
1027 if (pcibios_uninitialized_bridge_resource(bus, res)) {
1028 res->flags = 0;
1034 void pcibios_setup_bus_self(struct pci_bus *bus)
1038 /* Fix up the bus resources for P2P bridges */
1039 if (bus->self != NULL)
1040 pcibios_fixup_bridge(bus);
1042 /* Platform specific bus fixups. This is currently only used
1046 ppc_md.pcibios_fixup_bus(bus);
1048 /* Setup bus DMA mappings */
1049 phb = pci_bus_to_host(bus);
1050 if (phb->controller_ops.dma_bus_setup)
1051 phb->controller_ops.dma_bus_setup(bus);
1060 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1063 set_dma_ops(&dev->dev, pci_dma_ops);
1064 dev->dev.archdata.dma_offset = PCI_DRAM_OFFSET;
1067 phb = pci_bus_to_host(dev->bus);
1068 if (phb->controller_ops.dma_dev_setup)
1069 phb->controller_ops.dma_dev_setup(dev);
1089 d = dev_get_msi_domain(&dev->bus->dev);
1091 dev_set_msi_domain(&dev->dev, d);
1097 /* No special bus mastering setup handling */
1100 void pcibios_fixup_bus(struct pci_bus *bus)
1102 /* When called from the generic PCI probe, read PCI<->PCI bridge
1103 * bases. This is -not- called when generating the PCI tree from
1104 * the OF device-tree.
1106 pci_read_bridge_bases(bus);
1108 /* Now fixup the bus */
1109 pcibios_setup_bus_self(bus);
1116 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1124 * addresses to be allocated in the 0x000-0x0ff region
1128 * the low 10 bits of the IO address. The 0x00-0xff region
1130 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1131 * but we want to try to avoid allocating at 0x2900-0x2bff
1132 * which might have be mirrored at 0x0100-0x03ff..
1138 resource_size_t start = res->start;
1140 if (res->flags & IORESOURCE_IO) {
1161 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1162 if (p->end < res->start)
1164 if (res->end < p->start)
1166 if (p->start < res->start || p->end > res->end)
1167 return -1; /* not completely contained */
1172 return -1; /* didn't find any conflicting entries? */
1173 res->parent = parent;
1174 res->child = *firstpp;
1175 res->sibling = *pp;
1178 for (p = res->child; p != NULL; p = p->sibling) {
1179 p->parent = res;
1181 p->name, p, res->name);
1189 * On the other hand, we cannot just re-allocate all devices, as it would
1195 * - I/O or memory regions not configured
1196 * - regions configured, but not enabled in the command register
1197 * - bogus I/O addresses above 64K used
1198 * - expansion ROMs left enabled (this may sound harmless, but given
1204 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1219 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1225 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1226 pci_domain_nr(bus), bus->number);
1228 pci_bus_for_each_resource(bus, res, i) {
1229 if (!res || !res->flags || res->start > res->end || res->parent)
1233 if (res->flags & IORESOURCE_UNSET)
1236 if (bus->parent == NULL)
1237 pr = (res->flags & IORESOURCE_IO) ?
1240 pr = pci_find_parent_resource(bus->self, res);
1244 * bridge is transparent -- paulus
1250 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1251 bus->self ? pci_name(bus->self) : "PHB", bus->number,
1252 i, res, pr, (pr && pr->name) ? pr->name : "nil");
1254 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1255 struct pci_dev *dev = bus->self;
1273 i, bus->number);
1281 res->start = 0;
1282 res->end = -1;
1283 res->flags = 0;
1286 list_for_each_entry(b, &bus->children, node)
1292 struct resource *pr, *r = &dev->resource[idx];
1298 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1305 r->flags |= IORESOURCE_UNSET;
1306 r->end -= r->start;
1307 r->start = 0;
1321 r = &dev->resource[idx];
1322 if (r->parent) /* Already allocated */
1324 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1331 if (r->flags & IORESOURCE_IO)
1340 r = &dev->resource[PCI_ROM_RESOURCE];
1341 if (r->flags) {
1346 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1350 r->flags &= ~IORESOURCE_ROM_ENABLE;
1351 pci_write_config_dword(dev, dev->rom_base_reg,
1358 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1360 struct pci_controller *hose = pci_bus_to_host(bus);
1365 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1368 if (!(hose->io_resource.flags & IORESOURCE_IO))
1370 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1373 res->name = "Legacy IO";
1374 res->flags = IORESOURCE_IO;
1375 res->start = offset;
1376 res->end = (offset + 0xfff) & 0xfffffffful;
1378 if (request_resource(&hose->io_resource, res)) {
1381 pci_domain_nr(bus), bus->number, res);
1388 pres = &hose->mem_resources[i];
1389 offset = hose->mem_offset[i];
1390 if (!(pres->flags & IORESOURCE_MEM))
1393 if ((pres->start - offset) <= 0xa0000 &&
1394 (pres->end - offset) >= 0xbffff)
1401 res->name = "Legacy VGA memory";
1402 res->flags = IORESOURCE_MEM;
1403 res->start = 0xa0000 + offset;
1404 res->end = 0xbffff + offset;
1409 pci_domain_nr(bus), bus->number, res);
1428 * bus available resources to avoid allocating things on top of them
1446 * rest of the code later, for now, keep it as-is as our main
1447 * resource allocation function doesn't deal with sub-trees yet.
1449 void pcibios_claim_one_bus(struct pci_bus *bus)
1454 list_for_each_entry(dev, &bus->devices, bus_list) {
1459 if (r->parent || !r->start || !r->flags)
1472 list_for_each_entry(child_bus, &bus->children, node)
1481 * added to a bus, this include calling it for a PHB that is just
1484 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1486 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1487 pci_domain_nr(bus), bus->number);
1489 /* Allocate bus and devices resources */
1490 pcibios_allocate_bus_resources(bus);
1491 pcibios_claim_one_bus(bus);
1493 if (bus->self)
1494 pci_assign_unassigned_bridge_resources(bus->self);
1496 pci_assign_unassigned_bus_resources(bus);
1500 pci_bus_add_devices(bus);
1506 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1508 if (phb->controller_ops.enable_device_hook)
1509 if (!phb->controller_ops.enable_device_hook(dev))
1510 return -EINVAL;
1517 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1519 if (phb->controller_ops.disable_device)
1520 phb->controller_ops.disable_device(dev);
1525 return (unsigned long) hose->io_base_virt - _IO_BASE;
1536 res = &hose->io_resource;
1538 if (!res->flags) {
1541 hose->dn, hose->global_number);
1552 res = &hose->mem_resources[i];
1553 if (!res->flags)
1556 offset = hose->mem_offset[i];
1576 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1583 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1602 static struct pci_bus bus;
1605 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1607 bus.number = busnr;
1608 bus.sysdata = hose;
1609 bus.ops = hose? hose->ops: &null_pci_ops;
1610 return &bus;
1614 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1617 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1628 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1631 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1634 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1636 struct pci_controller *hose = bus->sysdata;
1638 return of_node_get(hose->dn);
1642 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1648 struct pci_bus *bus;
1649 struct device_node *node = hose->dn;
1657 /* Wire up PHB bus resources */
1660 hose->busn.start = hose->first_busno;
1661 hose->busn.end = hose->last_busno;
1662 hose->busn.flags = IORESOURCE_BUS;
1663 pci_add_resource(&resources, &hose->busn);
1665 /* Create an empty bus for the toplevel */
1666 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1667 hose->ops, hose, &resources);
1668 if (bus == NULL) {
1669 pr_err("Failed to create bus for PCI domain %04x\n",
1670 hose->global_number);
1674 hose->bus = bus;
1678 if (node && hose->controller_ops.probe_mode)
1679 mode = hose->controller_ops.probe_mode(bus);
1682 of_scan_bus(node, bus);
1685 pci_bus_update_busn_res_end(bus, 255);
1686 hose->last_busno = pci_scan_child_bus(bus);
1687 pci_bus_update_busn_res_end(bus, hose->last_busno);
1697 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1699 list_for_each_entry(child, &bus->children, node)
1707 int class = dev->class >> 8;
1709 int prog_if = dev->class & 0xf;
1714 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1716 (dev->bus->parent == NULL)) {
1718 r->start = 0;
1719 r->end = 0;
1720 r->flags = 0;