mips/pci/pcie-octeon.c

707 	union cvmx_npei_mem_access_subidx mem_access_subid;
895 	mem_access_subid.u64 = 0;
896 	mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
897 	mem_access_subid.s.nmerge = 1;	/* Due to an errata on pass 1 chips, no merging is allowed. */
898 	mem_access_subid.s.esr = 1;	/* Endian-swap for Reads. */
899 	mem_access_subid.s.esw = 1;	/* Endian-swap for Writes. */
900 	mem_access_subid.s.nsr = 0;	/* Enable Snooping for Reads. Octeon doesn't care, but devices might want this more conservative setting */
901 	mem_access_subid.s.nsw = 0;	/* Enable Snoop for Writes. */
902 	mem_access_subid.s.ror = 0;	/* Disable Relaxed Ordering for Reads. */
903 	mem_access_subid.s.row = 0;	/* Disable Relaxed Ordering for Writes. */
904 	mem_access_subid.s.ba = 0;	/* PCIe Address Bits <63:34>. */
911 		cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
912 		mem_access_subid.s.ba += 1; /* Set each SUBID to extend the addressable range */
1166 	union cvmx_sli_mem_access_subidx mem_access_subid;
1347 	mem_access_subid.u64 = 0;
1348 	mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
1349 	mem_access_subid.s.nmerge = 0;	/* Allow merging as it works on CN6XXX. */
1350 	mem_access_subid.s.esr = 1;	/* Endian-swap for Reads. */
1351 	mem_access_subid.s.esw = 1;	/* Endian-swap for Writes. */
1352 	mem_access_subid.s.wtype = 0;	/* "No snoop" and "Relaxed ordering" are not set */
1353 	mem_access_subid.s.rtype = 0;	/* "No snoop" and "Relaxed ordering" are not set */
1356 		mem_access_subid.cn68xx.ba = 0;
1358 		mem_access_subid.s.ba = 0;
1365 		cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
1367 		__cvmx_increment_ba(&mem_access_subid);