Lines Matching +full:snoop +full:- +full:ports

17 #include <asm/octeon/cvmx-npei-defs.h>
18 #include <asm/octeon/cvmx-pciercx-defs.h>
19 #include <asm/octeon/cvmx-pescx-defs.h>
20 #include <asm/octeon/cvmx-pexp-defs.h>
21 #include <asm/octeon/cvmx-pemx-defs.h>
22 #include <asm/octeon/cvmx-dpi-defs.h>
23 #include <asm/octeon/cvmx-sli-defs.h>
24 #include <asm/octeon/cvmx-sriox-defs.h>
25 #include <asm/octeon/cvmx-helper-errata.h>
26 #include <asm/octeon/pci-octeon.h>
89 uint64_t subdid:3; /* PCIe SubDID = 3-6 */
405 /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
421 /* Enable no snoop processing. Not used by Octeon */
425 /* Non-fatal error reporting enable. */
506 * Link Width Mode (PCIERCn_CFG452[LME]) - Set during
522 * Memory-mapped I/O BAR (PCIERCn_CFG008)
523 * Most applications should disable the memory-mapped I/O BAR by
556 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */
566 pciercx_cfg075.s.nfere = 1; /* Non-fatal error reporting enable. */
575 pciercx_cfg034.s.hpint_en = 1; /* Hot-plug interrupt enable. */
642 if (cvmx_get_cycle() - start_cycle > 2 * octeon_get_clock_rate()) {
644 return -1;
659 * from the PCIe spec table 3-4.
684 pmas->cn68xx.ba++;
686 pmas->s.ba++;
721 return -1;
732 return -1;
754 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) {
758 * both PCIe ports out of reset at the same time
771 /* Reset the ports */
777 /* Wait until pcie resets the ports. */
789 * The normal case: The PCIe ports are completely
809 /* Wait until pcie resets the ports. */
824 * Wait for PCIe reset to complete. Due to errata PCIE-700, we
845 return -1;
857 return -1;
862 * interface. This is an attempt to catch PCIE-813 on pass 1
869 return -1;
885 return -1;
898 mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */
899 mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
901 mem_access_subid.s.nsw = 0; /* Enable Snoop for Writes. */
907 * Setup mem access 12-15 for port 0, 16-19 for port 1,
921 cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i, pcie_port), -1);
922 cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i, pcie_port), -1);
925 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
939 /* Big endian swizzle for 32-bit PEXP_NCB register. */
954 * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take
965 * - PTLP_RO,CTLP_RO should normally be set (except for debug).
966 * - WAIT_COM=0 will likely work for all applications.
999 * reset is then performed. See PCIE-13340
1023 while (i--) {
1071 if ((cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) &&
1110 if (cvmx_get_cycle() - start_cycle > octeon_get_clock_rate())
1111 return -1;
1122 * from the PCIe spec table 3-4
1183 return -1;
1192 return -1;
1195 return -1;
1198 return -1;
1206 return -1;
1212 return -1;
1223 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1226 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1229 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1232 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1240 return -1;
1243 /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */
1278 /* Wait until pcie resets the ports. */
1301 return -1;
1309 /* Errata PCIE-14766 may cause the lower 6 bits to be randomly set on CN63XXp1 */
1336 return -1;
1350 mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */
1351 mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
1352 mem_access_subid.s.wtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
1353 mem_access_subid.s.rtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
1361 * Setup mem access 12-15 for port 0, 16-19 for port 1,
1376 cvmx_write_csr(CVMX_PEMX_P2P_BARX_START(i, pcie_port), -1);
1377 cvmx_write_csr(CVMX_PEMX_P2P_BARX_END(i, pcie_port), -1);
1380 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
1384 * Set Octeon's BAR2 to decode 0-2^41. Bar0 and Bar1 take
1394 * - PTLP_RO,CTLP_RO should normally be set (except for debug).
1395 * - WAIT_COM=0 will likely work for all applications.
1458 /* Above was cvmx-pcie.c, below original pcie.c */
1480 dev->bus && dev->bus->parent) {
1485 while (dev->bus && dev->bus->parent)
1486 dev = to_pci_dev(dev->bus->bridge);
1492 if ((dev->bus->number == 1) &&
1493 (dev->vendor == 0x10b5) && (dev->device == 0x8114)) {
1498 pin = ((pin - 3) & 3) + 1;
1502 * The -1 is because pin starts with one, not zero. It might
1506 return pin - 1 + OCTEON_IRQ_PCI_INT0;
1549 int bus_number = bus->number;
1561 if (bus->parent == NULL) {
1584 if ((bus->parent == NULL) && (devfn >> 3 != 0))
1597 * PCI-X slots. We need a new special checks to make
1598 * sure we only probe valid stuff. The PCIe->PCI-X
1600 * 0-1
1602 if ((bus->parent == NULL) && (devfn >= 2))
1605 * The PCI-X slots are device ID 2,3. Choose one of
1635 the required checks for running a Nitrox CN16XX-NHBX in the
1639 /* PLX bridge with 4 ports */
1740 int bus_number = bus->number;
1744 if ((bus->parent == NULL) && (enable_pcie_bus_num_war[pcie_port]))
1896 cvmx_pcie_get_io_base_address(1) -
1897 cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1;
1905 octeon_dummy_controller.io_map_base = -1;
1906 octeon_dummy_controller.mem_resource->start = (1ull<<48);
1907 octeon_dummy_controller.mem_resource->end = (1ull<<48);
1924 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
1948 * translates to 4GB-256MB, which is the same
1951 octeon_pcie0_controller.mem_resource->start =
1953 (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
1954 octeon_pcie0_controller.mem_resource->end =
1956 cvmx_pcie_get_mem_size(0) - 1;
1958 * Ports must be above 16KB for the ISA bus
1959 * filtering in the PCI-X to PCI bridge.
1961 octeon_pcie0_controller.io_resource->start = 4 << 10;
1962 octeon_pcie0_controller.io_resource->end =
1963 cvmx_pcie_get_io_size(0) - 1;
1972 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
1997 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
2025 cvmx_pcie_get_io_base_address(1) -
2030 * support. This normally translates to 4GB-256MB,
2033 octeon_pcie1_controller.mem_resource->start =
2034 cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
2036 octeon_pcie1_controller.mem_resource->end =
2038 cvmx_pcie_get_mem_size(1) - 1;
2040 * Ports must be above 16KB for the ISA bus filtering
2041 * in the PCI-X to PCI bridge.
2043 octeon_pcie1_controller.io_resource->start =
2044 cvmx_pcie_get_io_base_address(1) -
2046 octeon_pcie1_controller.io_resource->end =
2047 octeon_pcie1_controller.io_resource->start +
2048 cvmx_pcie_get_io_size(1) - 1;
2057 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
2066 * CN63XX pass 1_x/2.0 errata PCIe-15205 requires setting all