mips/kernel/pm-cps.c

188 static void cps_gen_cache_routine(u32 **pp, struct uasm_label **pl,
202 	UASM_i_LA(pp, GPR_T0, (long)CKSEG0);
206 		uasm_i_addiu(pp, GPR_T1, GPR_T0, cache_size);
208 		UASM_i_LA(pp, GPR_T1, (long)(CKSEG0 + cache_size));
211 	uasm_build_label(pl, *pp, lbl);
216 			uasm_i_cache(pp, op, 0, GPR_T0);
217 			uasm_i_addiu(pp, GPR_T0, GPR_T0, cache->linesz);
219 			uasm_i_cache(pp, op, i * cache->linesz, GPR_T0);
225 		uasm_i_addiu(pp, GPR_T0, GPR_T0, unroll_lines * cache->linesz);
228 	uasm_il_bne(pp, pr, GPR_T0, GPR_T1, lbl);
229 	uasm_i_nop(pp);
232 static int cps_gen_flush_fsb(u32 **pp, struct uasm_label **pl,
274 	uasm_i_mfc0(pp, GPR_T2, 25, (perf_counter * 2) + 0); /* PerfCtlN */
275 	uasm_i_mfc0(pp, GPR_T3, 25, (perf_counter * 2) + 1); /* PerfCntN */
278 	uasm_i_addiu(pp, GPR_T0, GPR_ZERO, (perf_event << 5) | 0xf);
279 	uasm_i_mtc0(pp, GPR_T0, 25, (perf_counter * 2) + 0); /* PerfCtlN */
280 	uasm_i_ehb(pp);
281 	uasm_i_mtc0(pp, GPR_ZERO, 25, (perf_counter * 2) + 1); /* PerfCntN */
282 	uasm_i_ehb(pp);
285 	UASM_i_LA(pp, GPR_T0, (long)CKSEG0);
288 	uasm_build_label(pl, *pp, lbl);
292 		uasm_i_lw(pp, GPR_ZERO, i * line_size * line_stride, GPR_T0);
299 		uasm_i_cache(pp, Hit_Invalidate_D,
301 		uasm_i_cache(pp, Hit_Writeback_Inv_SD,
306 	uasm_i_sync(pp, __SYNC_full);
307 	uasm_i_ehb(pp);
310 	uasm_i_mfc0(pp, GPR_T1, 25, (perf_counter * 2) + 1); /* PerfCntN */
313 	uasm_il_beqz(pp, pr, GPR_T1, lbl);
314 	uasm_i_nop(pp);
317 	uasm_i_mtc0(pp, GPR_T2, 25, (perf_counter * 2) + 0); /* PerfCtlN */
318 	uasm_i_ehb(pp);
319 	uasm_i_mtc0(pp, GPR_T3, 25, (perf_counter * 2) + 1); /* PerfCntN */
320 	uasm_i_ehb(pp);
325 static void cps_gen_set_top_bit(u32 **pp, struct uasm_label **pl,
329 	uasm_i_lui(pp, GPR_T0, uasm_rel_hi(0x80000000));
330 	uasm_build_label(pl, *pp, lbl);
331 	uasm_i_ll(pp, GPR_T1, 0, r_addr);
332 	uasm_i_or(pp, GPR_T1, GPR_T1, GPR_T0);
333 	uasm_i_sc(pp, GPR_T1, 0, r_addr);
334 	uasm_il_beqz(pp, pr, GPR_T1, lbl);
335 	uasm_i_nop(pp);