mips/kernel/perf_event_mipsxx.c

43 	 * MIPS CPUs vary in performance counters. They use this differently,
56 	 * MIPS performance counters are indexed starting from 0.
57 	 * CNTR_EVEN indicates the indexes of the counters to be used are
144 static unsigned int counters_total_to_per_cpu(unsigned int counters)
146 	return counters >> vpe_shift();
198 		 * The counters are unsigned, we must cast to truncate
332 		 * even and odd counters, whereas many other are only by
333 		 * even _or_ odd counters. This introduces an issue that
554 	/* Don't read disabled counters! */
570  * MIPS performance counters can be per-TC. The control registers can
574  * here we pause local counters and then grab a rwlock and leave the
575  * counters on other CPUs alone. If any counter interrupt raises while
576  * we own the write lock, simply pause local counters on that CPU and
578  * CPU after pausing local counters and before grabbing the lock.
604 			pr_warn("Unable to request IRQ%d for MIPS performance counters!\n",
631  * mipsxx/rm9000/loongson2 have different performance counters, they have
814 	int counters;
818 		counters = 2;
824 		counters = 4;
828 		counters = __n_counters();
831 	return counters;
836 	int counters = (int)(long)arg;
838 	switch (counters) {
908 	int counters = (int)(long)arg;
915 	switch (counters) {
1012 	 * counters don't differentiate between read and write
1093 	 * counters don't differentiate between read and write
1208 	 * counters don't differentiate between read and write
1263 	 * counters don't differentiate between read and write
1326 	 * counters don't differentiate between read and write
1379 	 * counters don't differentiate between read and write
1576 	unsigned int counters = mipspmu.num_counters;
1584 	 * First we pause the local counters, so that when we are locked
1585 	 * here, the counters are all paused. When it gets locked due to
1599 	for (n = counters - 1; n >= 0; n--) {
1693  * of even counters, and 128-255 for odd counters. Note that bit 7 is used to
1695  * the Event Num of 15 for odd counters (by referring to the user manual), then
1700  * events 0-511, where 0-255 are for the events of even counters, and 256-511
1701  * are for odd counters, so bit 8 is used to indicate the even/odd bank selector.
1892 	int counters, irq, pmu_type;
1894 	pr_info("Performance counters: ");
1896 	counters = n_counters();
1897 	if (counters == 0) {
1904 		counters = counters_total_to_per_cpu(counters);
1983 			counters = 2;
1988 			counters = 4;
1993 			counters = 4;
2015 			"counters, or not yet implemented.\n");
2019 	mipspmu.num_counters = counters;
2045 	on_each_cpu(reset_counters, (void *)(long)counters, 1);
2047 	pr_cont("%s PMU enabled, %d %d-bit counters available to each "
2048 		"CPU, irq %d%s\n", mipspmu.name, counters, counter_bits, irq,