Lines Matching refs:ir
76 * @ir: Instruction
78 static inline int mipsr6_emul(struct pt_regs *regs, u32 ir)
80 switch (MIPSInst_OPCODE(ir)) {
82 if (MIPSInst_RT(ir))
83 regs->regs[MIPSInst_RT(ir)] =
84 (s32)regs->regs[MIPSInst_RS(ir)] +
85 (s32)MIPSInst_SIMM(ir);
91 if (MIPSInst_RT(ir))
92 regs->regs[MIPSInst_RT(ir)] =
93 (s64)regs->regs[MIPSInst_RS(ir)] +
94 (s64)MIPSInst_SIMM(ir);
103 switch (MIPSInst_FUNC(ir)) {
105 if (MIPSInst_RD(ir))
106 regs->regs[MIPSInst_RD(ir)] =
107 regs->regs[MIPSInst_RS(ir)] |
108 regs->regs[MIPSInst_RT(ir)];
111 if (MIPSInst_RS(ir))
114 if (MIPSInst_RD(ir))
115 regs->regs[MIPSInst_RD(ir)] =
116 (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) <<
117 MIPSInst_FD(ir));
120 if (MIPSInst_RS(ir))
123 if (MIPSInst_RD(ir))
124 regs->regs[MIPSInst_RD(ir)] =
125 (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) >>
126 MIPSInst_FD(ir));
129 if (MIPSInst_FD(ir))
132 if (MIPSInst_RD(ir))
133 regs->regs[MIPSInst_RD(ir)] =
134 (s32)((u32)regs->regs[MIPSInst_RS(ir)] +
135 (u32)regs->regs[MIPSInst_RT(ir)]);
138 if (MIPSInst_FD(ir))
141 if (MIPSInst_RD(ir))
142 regs->regs[MIPSInst_RD(ir)] =
143 (s32)((u32)regs->regs[MIPSInst_RS(ir)] -
144 (u32)regs->regs[MIPSInst_RT(ir)]);
147 if (IS_ENABLED(CONFIG_32BIT) || MIPSInst_RS(ir))
150 if (MIPSInst_RD(ir))
151 regs->regs[MIPSInst_RD(ir)] =
152 (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) <<
153 MIPSInst_FD(ir));
156 if (IS_ENABLED(CONFIG_32BIT) || MIPSInst_RS(ir))
159 if (MIPSInst_RD(ir))
160 regs->regs[MIPSInst_RD(ir)] =
161 (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) >>
162 MIPSInst_FD(ir));
165 if (IS_ENABLED(CONFIG_32BIT) || MIPSInst_FD(ir))
168 if (MIPSInst_RD(ir))
169 regs->regs[MIPSInst_RD(ir)] =
170 (u64)regs->regs[MIPSInst_RS(ir)] +
171 (u64)regs->regs[MIPSInst_RT(ir)];
174 if (IS_ENABLED(CONFIG_32BIT) || MIPSInst_FD(ir))
177 if (MIPSInst_RD(ir))
178 regs->regs[MIPSInst_RD(ir)] =
179 (s64)((u64)regs->regs[MIPSInst_RS(ir)] -
180 (u64)regs->regs[MIPSInst_RT(ir)]);
186 ir, MIPSInst_OPCODE(ir));
195 * @ir: Instruction
199 static int movf_func(struct pt_regs *regs, u32 ir)
205 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
207 if (((csr & cond) == 0) && MIPSInst_RD(ir))
208 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
218 * @ir: Instruction
222 static int movt_func(struct pt_regs *regs, u32 ir)
228 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
230 if (((csr & cond) != 0) && MIPSInst_RD(ir))
231 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
241 * @ir: Instruction
247 static int jr_func(struct pt_regs *regs, u32 ir)
300 * @ir: Instruction
304 static int movz_func(struct pt_regs *regs, u32 ir)
306 if (((regs->regs[MIPSInst_RT(ir)]) == 0) && MIPSInst_RD(ir))
307 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
316 * @ir: Instruction
320 static int movn_func(struct pt_regs *regs, u32 ir)
322 if (((regs->regs[MIPSInst_RT(ir)]) != 0) && MIPSInst_RD(ir))
323 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
332 * @ir: Instruction
336 static int mfhi_func(struct pt_regs *regs, u32 ir)
338 if (MIPSInst_RD(ir))
339 regs->regs[MIPSInst_RD(ir)] = regs->hi;
349 * @ir: Instruction
353 static int mthi_func(struct pt_regs *regs, u32 ir)
355 regs->hi = regs->regs[MIPSInst_RS(ir)];
365 * @ir: Instruction
369 static int mflo_func(struct pt_regs *regs, u32 ir)
371 if (MIPSInst_RD(ir))
372 regs->regs[MIPSInst_RD(ir)] = regs->lo;
382 * @ir: Instruction
386 static int mtlo_func(struct pt_regs *regs, u32 ir)
388 regs->lo = regs->regs[MIPSInst_RS(ir)];
398 * @ir: Instruction
402 static int mult_func(struct pt_regs *regs, u32 ir)
407 rt = regs->regs[MIPSInst_RT(ir)];
408 rs = regs->regs[MIPSInst_RS(ir)];
425 * @ir: Instruction
429 static int multu_func(struct pt_regs *regs, u32 ir)
434 rt = regs->regs[MIPSInst_RT(ir)];
435 rs = regs->regs[MIPSInst_RS(ir)];
449 * @ir: Instruction
453 static int div_func(struct pt_regs *regs, u32 ir)
457 rt = regs->regs[MIPSInst_RT(ir)];
458 rs = regs->regs[MIPSInst_RS(ir)];
471 * @ir: Instruction
475 static int divu_func(struct pt_regs *regs, u32 ir)
479 rt = regs->regs[MIPSInst_RT(ir)];
480 rs = regs->regs[MIPSInst_RS(ir)];
493 * @ir: Instruction
497 static int dmult_func(struct pt_regs *regs, u32 ir)
505 rt = regs->regs[MIPSInst_RT(ir)];
506 rs = regs->regs[MIPSInst_RS(ir)];
525 * @ir: Instruction
529 static int dmultu_func(struct pt_regs *regs, u32 ir)
537 rt = regs->regs[MIPSInst_RT(ir)];
538 rs = regs->regs[MIPSInst_RS(ir)];
557 * @ir: Instruction
561 static int ddiv_func(struct pt_regs *regs, u32 ir)
568 rt = regs->regs[MIPSInst_RT(ir)];
569 rs = regs->regs[MIPSInst_RS(ir)];
582 * @ir: Instruction
586 static int ddivu_func(struct pt_regs *regs, u32 ir)
593 rt = regs->regs[MIPSInst_RT(ir)];
594 rs = regs->regs[MIPSInst_RS(ir)];
629 * @ir: Instruction
633 static int madd_func(struct pt_regs *regs, u32 ir)
638 rt = regs->regs[MIPSInst_RT(ir)];
639 rs = regs->regs[MIPSInst_RS(ir)];
658 * @ir: Instruction
662 static int maddu_func(struct pt_regs *regs, u32 ir)
667 rt = regs->regs[MIPSInst_RT(ir)];
668 rs = regs->regs[MIPSInst_RS(ir)];
687 * @ir: Instruction
691 static int msub_func(struct pt_regs *regs, u32 ir)
696 rt = regs->regs[MIPSInst_RT(ir)];
697 rs = regs->regs[MIPSInst_RS(ir)];
716 * @ir: Instruction
720 static int msubu_func(struct pt_regs *regs, u32 ir)
725 rt = regs->regs[MIPSInst_RT(ir)];
726 rs = regs->regs[MIPSInst_RS(ir)];
745 * @ir: Instruction
749 static int mul_func(struct pt_regs *regs, u32 ir)
754 if (!MIPSInst_RD(ir))
756 rt = regs->regs[MIPSInst_RT(ir)];
757 rs = regs->regs[MIPSInst_RS(ir)];
761 regs->regs[MIPSInst_RD(ir)] = (s64)rs;
771 * @ir: Instruction
775 static int clz_func(struct pt_regs *regs, u32 ir)
780 if (!MIPSInst_RD(ir))
783 rs = regs->regs[MIPSInst_RS(ir)];
785 regs->regs[MIPSInst_RD(ir)] = res;
795 * @ir: Instruction
800 static int clo_func(struct pt_regs *regs, u32 ir)
805 if (!MIPSInst_RD(ir))
808 rs = regs->regs[MIPSInst_RS(ir)];
810 regs->regs[MIPSInst_RD(ir)] = res;
820 * @ir: Instruction
824 static int dclz_func(struct pt_regs *regs, u32 ir)
832 if (!MIPSInst_RD(ir))
835 rs = regs->regs[MIPSInst_RS(ir)];
837 regs->regs[MIPSInst_RD(ir)] = res;
847 * @ir: Instruction
851 static int dclo_func(struct pt_regs *regs, u32 ir)
859 if (!MIPSInst_RD(ir))
862 rs = regs->regs[MIPSInst_RS(ir)];
864 regs->regs[MIPSInst_RD(ir)] = res;