Lines Matching +full:- +full:n
28 #include <asm/mips-r2-to-r6-emul.h>
65 pr_info("MIPS R2-to-R6 Emulator Enabled!");
72 * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot
83 regs->regs[MIPSInst_RT(ir)] =
84 (s32)regs->regs[MIPSInst_RS(ir)] +
92 regs->regs[MIPSInst_RT(ir)] =
93 (s64)regs->regs[MIPSInst_RS(ir)] +
101 return -SIGFPE;
106 regs->regs[MIPSInst_RD(ir)] =
107 regs->regs[MIPSInst_RS(ir)] |
108 regs->regs[MIPSInst_RT(ir)];
115 regs->regs[MIPSInst_RD(ir)] =
116 (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) <<
124 regs->regs[MIPSInst_RD(ir)] =
125 (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) >>
133 regs->regs[MIPSInst_RD(ir)] =
134 (s32)((u32)regs->regs[MIPSInst_RS(ir)] +
135 (u32)regs->regs[MIPSInst_RT(ir)]);
142 regs->regs[MIPSInst_RD(ir)] =
143 (s32)((u32)regs->regs[MIPSInst_RS(ir)] -
144 (u32)regs->regs[MIPSInst_RT(ir)]);
151 regs->regs[MIPSInst_RD(ir)] =
152 (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) <<
160 regs->regs[MIPSInst_RD(ir)] =
161 (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) >>
169 regs->regs[MIPSInst_RD(ir)] =
170 (u64)regs->regs[MIPSInst_RS(ir)] +
171 (u64)regs->regs[MIPSInst_RT(ir)];
178 regs->regs[MIPSInst_RD(ir)] =
179 (s64)((u64)regs->regs[MIPSInst_RS(ir)] -
180 (u64)regs->regs[MIPSInst_RT(ir)]);
185 pr_debug("No fastpath BD emulation for instruction 0x%08x (op: %02x)\n",
193 * movf_func - Emulate a MOVF instruction
204 csr = current->thread.fpu.fcr31;
208 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
216 * movt_func - Emulate a MOVT instruction
227 csr = current->thread.fpu.fcr31;
231 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
239 * jr_func - Emulate a JR instruction.
257 nepc = regs->cp0_epc;
259 regs->cp0_epc -= 4;
260 epc = regs->cp0_epc;
268 cepc = regs->cp0_epc;
280 * Negative err means FPU instruction in BD-slot,
281 * Zero err means 'BD-slot emulation done'
286 regs->cp0_epc = nepc;
298 * movz_func - Emulate a MOVZ instruction
306 if (((regs->regs[MIPSInst_RT(ir)]) == 0) && MIPSInst_RD(ir))
307 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
314 * movn_func - Emulate a MOVZ instruction
322 if (((regs->regs[MIPSInst_RT(ir)]) != 0) && MIPSInst_RD(ir))
323 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
330 * mfhi_func - Emulate a MFHI instruction
339 regs->regs[MIPSInst_RD(ir)] = regs->hi;
347 * mthi_func - Emulate a MTHI instruction
355 regs->hi = regs->regs[MIPSInst_RS(ir)];
363 * mflo_func - Emulate a MFLO instruction
372 regs->regs[MIPSInst_RD(ir)] = regs->lo;
380 * mtlo_func - Emulate a MTLO instruction
388 regs->lo = regs->regs[MIPSInst_RS(ir)];
396 * mult_func - Emulate a MULT instruction
407 rt = regs->regs[MIPSInst_RT(ir)];
408 rs = regs->regs[MIPSInst_RS(ir)];
412 regs->lo = (s64)rs;
415 regs->hi = res;
423 * multu_func - Emulate a MULTU instruction
434 rt = regs->regs[MIPSInst_RT(ir)];
435 rs = regs->regs[MIPSInst_RS(ir)];
438 regs->lo = (s64)(s32)rt;
439 regs->hi = (s64)(s32)(res >> 32);
447 * div_func - Emulate a DIV instruction
457 rt = regs->regs[MIPSInst_RT(ir)];
458 rs = regs->regs[MIPSInst_RS(ir)];
460 regs->lo = (s64)(rs / rt);
461 regs->hi = (s64)(rs % rt);
469 * divu_func - Emulate a DIVU instruction
479 rt = regs->regs[MIPSInst_RT(ir)];
480 rs = regs->regs[MIPSInst_RS(ir)];
482 regs->lo = (s64)(rs / rt);
483 regs->hi = (s64)(rs % rt);
491 * dmult_func - Emulate a DMULT instruction
495 * Returns 0 on success or SIGILL for 32-bit kernels.
505 rt = regs->regs[MIPSInst_RT(ir)];
506 rs = regs->regs[MIPSInst_RS(ir)];
509 regs->lo = res;
511 "dmuh %0, %1, %2\t\n"
515 regs->hi = res;
523 * dmultu_func - Emulate a DMULTU instruction
527 * Returns 0 on success or SIGILL for 32-bit kernels.
537 rt = regs->regs[MIPSInst_RT(ir)];
538 rs = regs->regs[MIPSInst_RS(ir)];
541 regs->lo = res;
543 "dmuhu %0, %1, %2\t\n"
547 regs->hi = res;
555 * ddiv_func - Emulate a DDIV instruction
559 * Returns 0 on success or SIGILL for 32-bit kernels.
568 rt = regs->regs[MIPSInst_RT(ir)];
569 rs = regs->regs[MIPSInst_RS(ir)];
571 regs->lo = rs / rt;
572 regs->hi = rs % rt;
580 * ddivu_func - Emulate a DDIVU instruction
584 * Returns 0 on success or SIGILL for 32-bit kernels.
593 rt = regs->regs[MIPSInst_RT(ir)];
594 rs = regs->regs[MIPSInst_RS(ir)];
596 regs->lo = rs / rt;
597 regs->hi = rs % rt;
627 * madd_func - Emulate a MADD instruction
638 rt = regs->regs[MIPSInst_RT(ir)];
639 rs = regs->regs[MIPSInst_RS(ir)];
641 rt = regs->hi;
642 rs = regs->lo;
646 regs->lo = (s64)rt;
648 regs->hi = (s64)rs;
656 * maddu_func - Emulate a MADDU instruction
667 rt = regs->regs[MIPSInst_RT(ir)];
668 rs = regs->regs[MIPSInst_RS(ir)];
670 rt = regs->hi;
671 rs = regs->lo;
675 regs->lo = (s64)(s32)rt;
677 regs->hi = (s64)(s32)rs;
685 * msub_func - Emulate a MSUB instruction
696 rt = regs->regs[MIPSInst_RT(ir)];
697 rs = regs->regs[MIPSInst_RS(ir)];
699 rt = regs->hi;
700 rs = regs->lo;
701 res = ((((s64)rt) << 32) | (u32)rs) - res;
704 regs->lo = (s64)rt;
706 regs->hi = (s64)rs;
714 * msubu_func - Emulate a MSUBU instruction
725 rt = regs->regs[MIPSInst_RT(ir)];
726 rs = regs->regs[MIPSInst_RS(ir)];
728 rt = regs->hi;
729 rs = regs->lo;
730 res = ((((s64)rt) << 32) | (u32)rs) - res;
733 regs->lo = (s64)(s32)rt;
735 regs->hi = (s64)(s32)rs;
743 * mul_func - Emulate a MUL instruction
756 rt = regs->regs[MIPSInst_RT(ir)];
757 rs = regs->regs[MIPSInst_RS(ir)];
761 regs->regs[MIPSInst_RD(ir)] = (s64)rs;
769 * clz_func - Emulate a CLZ instruction
783 rs = regs->regs[MIPSInst_RS(ir)];
785 regs->regs[MIPSInst_RD(ir)] = res;
793 * clo_func - Emulate a CLO instruction
808 rs = regs->regs[MIPSInst_RS(ir)];
810 regs->regs[MIPSInst_RD(ir)] = res;
818 * dclz_func - Emulate a DCLZ instruction
835 rs = regs->regs[MIPSInst_RS(ir)];
837 regs->regs[MIPSInst_RD(ir)] = res;
845 * dclo_func - Emulate a DCLO instruction
862 rs = regs->regs[MIPSInst_RS(ir)];
864 regs->regs[MIPSInst_RD(ir)] = res;
891 for (p = table; p->func; p++) {
892 if ((inst & p->mask) == p->code) {
893 err = (p->func)(regs, inst);
917 r31 = regs->regs[31];
918 epc = regs->cp0_epc;
924 pr_debug("Emulating the 0x%08x R2 instruction @ 0x%08lx (pass=%d))\n",
932 regs->cp0_cause |= CAUSEF_BD;
944 if ((long)regs->regs[rs] >= MIPSInst_SIMM(inst))
951 if (regs->regs[rs] >= MIPSInst_UIMM(inst))
958 if ((long)regs->regs[rs] < MIPSInst_SIMM(inst))
965 if (regs->regs[rs] < MIPSInst_UIMM(inst))
972 if (regs->regs[rs] == MIPSInst_SIMM(inst))
979 if (regs->regs[rs] != MIPSInst_SIMM(inst))
993 regs->regs[31] = r31;
994 regs->cp0_epc = epc;
1000 cpc = regs->cp0_epc;
1031 regs->cp0_cause |= CAUSEF_BD;
1050 regs->regs[31] = r31;
1051 regs->cp0_epc = epc;
1055 cpc = regs->cp0_epc;
1080 regs->cp0_cause |= CAUSEF_BD;
1094 regs->regs[31] = r31;
1095 regs->cp0_epc = epc;
1119 regs->regs[31] = r31;
1120 regs->cp0_epc = epc;
1126 cpc = regs->cp0_epc;
1157 regs->cp0_cause |= CAUSEF_BD;
1175 regs->regs[31] = r31;
1176 regs->cp0_epc = epc;
1178 err = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0,
1185 *fcr31 = res = mask_fcr31_x(current->thread.fpu.fcr31);
1186 current->thread.fpu.fcr31 &= ~res;
1189 * this is a tricky issue - lose_fpu() uses LL/SC atomics
1193 * more often than LL-FPU-SC and I prefer loop here until
1199 current->thread.cp0_baduaddr = (unsigned long)fault_addr;
1206 rt = regs->regs[MIPSInst_RT(inst)];
1207 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1209 current->thread.cp0_baduaddr = vaddr;
1214 " .set push\n"
1215 " .set reorder\n"
1217 "1:" LB "%1, 0(%2)\n"
1218 INS "%0, %1, 24, 8\n"
1219 " andi %1, %2, 0x3\n"
1220 " beq $0, %1, 9f\n"
1221 ADDIU "%2, %2, -1\n"
1222 "2:" LB "%1, 0(%2)\n"
1223 INS "%0, %1, 16, 8\n"
1224 " andi %1, %2, 0x3\n"
1225 " beq $0, %1, 9f\n"
1226 ADDIU "%2, %2, -1\n"
1227 "3:" LB "%1, 0(%2)\n"
1228 INS "%0, %1, 8, 8\n"
1229 " andi %1, %2, 0x3\n"
1230 " beq $0, %1, 9f\n"
1231 ADDIU "%2, %2, -1\n"
1232 "4:" LB "%1, 0(%2)\n"
1233 INS "%0, %1, 0, 8\n"
1235 "1:" LB "%1, 0(%2)\n"
1236 INS "%0, %1, 24, 8\n"
1237 ADDIU "%2, %2, 1\n"
1238 " andi %1, %2, 0x3\n"
1239 " beq $0, %1, 9f\n"
1240 "2:" LB "%1, 0(%2)\n"
1241 INS "%0, %1, 16, 8\n"
1242 ADDIU "%2, %2, 1\n"
1243 " andi %1, %2, 0x3\n"
1244 " beq $0, %1, 9f\n"
1245 "3:" LB "%1, 0(%2)\n"
1246 INS "%0, %1, 8, 8\n"
1247 ADDIU "%2, %2, 1\n"
1248 " andi %1, %2, 0x3\n"
1249 " beq $0, %1, 9f\n"
1250 "4:" LB "%1, 0(%2)\n"
1251 INS "%0, %1, 0, 8\n"
1253 "9: sll %0, %0, 0\n"
1254 "10:\n"
1255 " .insn\n"
1256 " .section .fixup,\"ax\"\n"
1257 "8: li %3,%4\n"
1258 " j 10b\n"
1259 " .previous\n"
1260 " .section __ex_table,\"a\"\n"
1261 STR(PTR_WD) " 1b,8b\n"
1262 STR(PTR_WD) " 2b,8b\n"
1263 STR(PTR_WD) " 3b,8b\n"
1264 STR(PTR_WD) " 4b,8b\n"
1265 " .previous\n"
1266 " .set pop\n"
1272 regs->regs[MIPSInst_RT(inst)] = rt;
1279 rt = regs->regs[MIPSInst_RT(inst)];
1280 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1282 current->thread.cp0_baduaddr = vaddr;
1287 " .set push\n"
1288 " .set reorder\n"
1290 "1:" LB "%1, 0(%2)\n"
1291 INS "%0, %1, 0, 8\n"
1292 ADDIU "%2, %2, 1\n"
1293 " andi %1, %2, 0x3\n"
1294 " beq $0, %1, 9f\n"
1295 "2:" LB "%1, 0(%2)\n"
1296 INS "%0, %1, 8, 8\n"
1297 ADDIU "%2, %2, 1\n"
1298 " andi %1, %2, 0x3\n"
1299 " beq $0, %1, 9f\n"
1300 "3:" LB "%1, 0(%2)\n"
1301 INS "%0, %1, 16, 8\n"
1302 ADDIU "%2, %2, 1\n"
1303 " andi %1, %2, 0x3\n"
1304 " beq $0, %1, 9f\n"
1305 "4:" LB "%1, 0(%2)\n"
1306 INS "%0, %1, 24, 8\n"
1307 " sll %0, %0, 0\n"
1309 "1:" LB "%1, 0(%2)\n"
1310 INS "%0, %1, 0, 8\n"
1311 " andi %1, %2, 0x3\n"
1312 " beq $0, %1, 9f\n"
1313 ADDIU "%2, %2, -1\n"
1314 "2:" LB "%1, 0(%2)\n"
1315 INS "%0, %1, 8, 8\n"
1316 " andi %1, %2, 0x3\n"
1317 " beq $0, %1, 9f\n"
1318 ADDIU "%2, %2, -1\n"
1319 "3:" LB "%1, 0(%2)\n"
1320 INS "%0, %1, 16, 8\n"
1321 " andi %1, %2, 0x3\n"
1322 " beq $0, %1, 9f\n"
1323 ADDIU "%2, %2, -1\n"
1324 "4:" LB "%1, 0(%2)\n"
1325 INS "%0, %1, 24, 8\n"
1326 " sll %0, %0, 0\n"
1328 "9:\n"
1329 "10:\n"
1330 " .insn\n"
1331 " .section .fixup,\"ax\"\n"
1332 "8: li %3,%4\n"
1333 " j 10b\n"
1334 " .previous\n"
1335 " .section __ex_table,\"a\"\n"
1336 STR(PTR_WD) " 1b,8b\n"
1337 STR(PTR_WD) " 2b,8b\n"
1338 STR(PTR_WD) " 3b,8b\n"
1339 STR(PTR_WD) " 4b,8b\n"
1340 " .previous\n"
1341 " .set pop\n"
1346 regs->regs[MIPSInst_RT(inst)] = rt;
1353 rt = regs->regs[MIPSInst_RT(inst)];
1354 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1356 current->thread.cp0_baduaddr = vaddr;
1361 " .set push\n"
1362 " .set reorder\n"
1364 EXT "%1, %0, 24, 8\n"
1365 "1:" SB "%1, 0(%2)\n"
1366 " andi %1, %2, 0x3\n"
1367 " beq $0, %1, 9f\n"
1368 ADDIU "%2, %2, -1\n"
1369 EXT "%1, %0, 16, 8\n"
1370 "2:" SB "%1, 0(%2)\n"
1371 " andi %1, %2, 0x3\n"
1372 " beq $0, %1, 9f\n"
1373 ADDIU "%2, %2, -1\n"
1374 EXT "%1, %0, 8, 8\n"
1375 "3:" SB "%1, 0(%2)\n"
1376 " andi %1, %2, 0x3\n"
1377 " beq $0, %1, 9f\n"
1378 ADDIU "%2, %2, -1\n"
1379 EXT "%1, %0, 0, 8\n"
1380 "4:" SB "%1, 0(%2)\n"
1382 EXT "%1, %0, 24, 8\n"
1383 "1:" SB "%1, 0(%2)\n"
1384 ADDIU "%2, %2, 1\n"
1385 " andi %1, %2, 0x3\n"
1386 " beq $0, %1, 9f\n"
1387 EXT "%1, %0, 16, 8\n"
1388 "2:" SB "%1, 0(%2)\n"
1389 ADDIU "%2, %2, 1\n"
1390 " andi %1, %2, 0x3\n"
1391 " beq $0, %1, 9f\n"
1392 EXT "%1, %0, 8, 8\n"
1393 "3:" SB "%1, 0(%2)\n"
1394 ADDIU "%2, %2, 1\n"
1395 " andi %1, %2, 0x3\n"
1396 " beq $0, %1, 9f\n"
1397 EXT "%1, %0, 0, 8\n"
1398 "4:" SB "%1, 0(%2)\n"
1400 "9:\n"
1401 " .insn\n"
1402 " .section .fixup,\"ax\"\n"
1403 "8: li %3,%4\n"
1404 " j 9b\n"
1405 " .previous\n"
1406 " .section __ex_table,\"a\"\n"
1407 STR(PTR_WD) " 1b,8b\n"
1408 STR(PTR_WD) " 2b,8b\n"
1409 STR(PTR_WD) " 3b,8b\n"
1410 STR(PTR_WD) " 4b,8b\n"
1411 " .previous\n"
1412 " .set pop\n"
1423 rt = regs->regs[MIPSInst_RT(inst)];
1424 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1426 current->thread.cp0_baduaddr = vaddr;
1431 " .set push\n"
1432 " .set reorder\n"
1434 EXT "%1, %0, 0, 8\n"
1435 "1:" SB "%1, 0(%2)\n"
1436 ADDIU "%2, %2, 1\n"
1437 " andi %1, %2, 0x3\n"
1438 " beq $0, %1, 9f\n"
1439 EXT "%1, %0, 8, 8\n"
1440 "2:" SB "%1, 0(%2)\n"
1441 ADDIU "%2, %2, 1\n"
1442 " andi %1, %2, 0x3\n"
1443 " beq $0, %1, 9f\n"
1444 EXT "%1, %0, 16, 8\n"
1445 "3:" SB "%1, 0(%2)\n"
1446 ADDIU "%2, %2, 1\n"
1447 " andi %1, %2, 0x3\n"
1448 " beq $0, %1, 9f\n"
1449 EXT "%1, %0, 24, 8\n"
1450 "4:" SB "%1, 0(%2)\n"
1452 EXT "%1, %0, 0, 8\n"
1453 "1:" SB "%1, 0(%2)\n"
1454 " andi %1, %2, 0x3\n"
1455 " beq $0, %1, 9f\n"
1456 ADDIU "%2, %2, -1\n"
1457 EXT "%1, %0, 8, 8\n"
1458 "2:" SB "%1, 0(%2)\n"
1459 " andi %1, %2, 0x3\n"
1460 " beq $0, %1, 9f\n"
1461 ADDIU "%2, %2, -1\n"
1462 EXT "%1, %0, 16, 8\n"
1463 "3:" SB "%1, 0(%2)\n"
1464 " andi %1, %2, 0x3\n"
1465 " beq $0, %1, 9f\n"
1466 ADDIU "%2, %2, -1\n"
1467 EXT "%1, %0, 24, 8\n"
1468 "4:" SB "%1, 0(%2)\n"
1470 "9:\n"
1471 " .insn\n"
1472 " .section .fixup,\"ax\"\n"
1473 "8: li %3,%4\n"
1474 " j 9b\n"
1475 " .previous\n"
1476 " .section __ex_table,\"a\"\n"
1477 STR(PTR_WD) " 1b,8b\n"
1478 STR(PTR_WD) " 2b,8b\n"
1479 STR(PTR_WD) " 3b,8b\n"
1480 STR(PTR_WD) " 4b,8b\n"
1481 " .previous\n"
1482 " .set pop\n"
1498 rt = regs->regs[MIPSInst_RT(inst)];
1499 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1501 current->thread.cp0_baduaddr = vaddr;
1506 " .set push\n"
1507 " .set reorder\n"
1509 "1: lb %1, 0(%2)\n"
1510 " dinsu %0, %1, 56, 8\n"
1511 " andi %1, %2, 0x7\n"
1512 " beq $0, %1, 9f\n"
1513 " daddiu %2, %2, -1\n"
1514 "2: lb %1, 0(%2)\n"
1515 " dinsu %0, %1, 48, 8\n"
1516 " andi %1, %2, 0x7\n"
1517 " beq $0, %1, 9f\n"
1518 " daddiu %2, %2, -1\n"
1519 "3: lb %1, 0(%2)\n"
1520 " dinsu %0, %1, 40, 8\n"
1521 " andi %1, %2, 0x7\n"
1522 " beq $0, %1, 9f\n"
1523 " daddiu %2, %2, -1\n"
1524 "4: lb %1, 0(%2)\n"
1525 " dinsu %0, %1, 32, 8\n"
1526 " andi %1, %2, 0x7\n"
1527 " beq $0, %1, 9f\n"
1528 " daddiu %2, %2, -1\n"
1529 "5: lb %1, 0(%2)\n"
1530 " dins %0, %1, 24, 8\n"
1531 " andi %1, %2, 0x7\n"
1532 " beq $0, %1, 9f\n"
1533 " daddiu %2, %2, -1\n"
1534 "6: lb %1, 0(%2)\n"
1535 " dins %0, %1, 16, 8\n"
1536 " andi %1, %2, 0x7\n"
1537 " beq $0, %1, 9f\n"
1538 " daddiu %2, %2, -1\n"
1539 "7: lb %1, 0(%2)\n"
1540 " dins %0, %1, 8, 8\n"
1541 " andi %1, %2, 0x7\n"
1542 " beq $0, %1, 9f\n"
1543 " daddiu %2, %2, -1\n"
1544 "0: lb %1, 0(%2)\n"
1545 " dins %0, %1, 0, 8\n"
1547 "1: lb %1, 0(%2)\n"
1548 " dinsu %0, %1, 56, 8\n"
1549 " daddiu %2, %2, 1\n"
1550 " andi %1, %2, 0x7\n"
1551 " beq $0, %1, 9f\n"
1552 "2: lb %1, 0(%2)\n"
1553 " dinsu %0, %1, 48, 8\n"
1554 " daddiu %2, %2, 1\n"
1555 " andi %1, %2, 0x7\n"
1556 " beq $0, %1, 9f\n"
1557 "3: lb %1, 0(%2)\n"
1558 " dinsu %0, %1, 40, 8\n"
1559 " daddiu %2, %2, 1\n"
1560 " andi %1, %2, 0x7\n"
1561 " beq $0, %1, 9f\n"
1562 "4: lb %1, 0(%2)\n"
1563 " dinsu %0, %1, 32, 8\n"
1564 " daddiu %2, %2, 1\n"
1565 " andi %1, %2, 0x7\n"
1566 " beq $0, %1, 9f\n"
1567 "5: lb %1, 0(%2)\n"
1568 " dins %0, %1, 24, 8\n"
1569 " daddiu %2, %2, 1\n"
1570 " andi %1, %2, 0x7\n"
1571 " beq $0, %1, 9f\n"
1572 "6: lb %1, 0(%2)\n"
1573 " dins %0, %1, 16, 8\n"
1574 " daddiu %2, %2, 1\n"
1575 " andi %1, %2, 0x7\n"
1576 " beq $0, %1, 9f\n"
1577 "7: lb %1, 0(%2)\n"
1578 " dins %0, %1, 8, 8\n"
1579 " daddiu %2, %2, 1\n"
1580 " andi %1, %2, 0x7\n"
1581 " beq $0, %1, 9f\n"
1582 "0: lb %1, 0(%2)\n"
1583 " dins %0, %1, 0, 8\n"
1585 "9:\n"
1586 " .insn\n"
1587 " .section .fixup,\"ax\"\n"
1588 "8: li %3,%4\n"
1589 " j 9b\n"
1590 " .previous\n"
1591 " .section __ex_table,\"a\"\n"
1592 STR(PTR_WD) " 1b,8b\n"
1593 STR(PTR_WD) " 2b,8b\n"
1594 STR(PTR_WD) " 3b,8b\n"
1595 STR(PTR_WD) " 4b,8b\n"
1596 STR(PTR_WD) " 5b,8b\n"
1597 STR(PTR_WD) " 6b,8b\n"
1598 STR(PTR_WD) " 7b,8b\n"
1599 STR(PTR_WD) " 0b,8b\n"
1600 " .previous\n"
1601 " .set pop\n"
1606 regs->regs[MIPSInst_RT(inst)] = rt;
1617 rt = regs->regs[MIPSInst_RT(inst)];
1618 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1620 current->thread.cp0_baduaddr = vaddr;
1625 " .set push\n"
1626 " .set reorder\n"
1628 "1: lb %1, 0(%2)\n"
1629 " dins %0, %1, 0, 8\n"
1630 " daddiu %2, %2, 1\n"
1631 " andi %1, %2, 0x7\n"
1632 " beq $0, %1, 9f\n"
1633 "2: lb %1, 0(%2)\n"
1634 " dins %0, %1, 8, 8\n"
1635 " daddiu %2, %2, 1\n"
1636 " andi %1, %2, 0x7\n"
1637 " beq $0, %1, 9f\n"
1638 "3: lb %1, 0(%2)\n"
1639 " dins %0, %1, 16, 8\n"
1640 " daddiu %2, %2, 1\n"
1641 " andi %1, %2, 0x7\n"
1642 " beq $0, %1, 9f\n"
1643 "4: lb %1, 0(%2)\n"
1644 " dins %0, %1, 24, 8\n"
1645 " daddiu %2, %2, 1\n"
1646 " andi %1, %2, 0x7\n"
1647 " beq $0, %1, 9f\n"
1648 "5: lb %1, 0(%2)\n"
1649 " dinsu %0, %1, 32, 8\n"
1650 " daddiu %2, %2, 1\n"
1651 " andi %1, %2, 0x7\n"
1652 " beq $0, %1, 9f\n"
1653 "6: lb %1, 0(%2)\n"
1654 " dinsu %0, %1, 40, 8\n"
1655 " daddiu %2, %2, 1\n"
1656 " andi %1, %2, 0x7\n"
1657 " beq $0, %1, 9f\n"
1658 "7: lb %1, 0(%2)\n"
1659 " dinsu %0, %1, 48, 8\n"
1660 " daddiu %2, %2, 1\n"
1661 " andi %1, %2, 0x7\n"
1662 " beq $0, %1, 9f\n"
1663 "0: lb %1, 0(%2)\n"
1664 " dinsu %0, %1, 56, 8\n"
1666 "1: lb %1, 0(%2)\n"
1667 " dins %0, %1, 0, 8\n"
1668 " andi %1, %2, 0x7\n"
1669 " beq $0, %1, 9f\n"
1670 " daddiu %2, %2, -1\n"
1671 "2: lb %1, 0(%2)\n"
1672 " dins %0, %1, 8, 8\n"
1673 " andi %1, %2, 0x7\n"
1674 " beq $0, %1, 9f\n"
1675 " daddiu %2, %2, -1\n"
1676 "3: lb %1, 0(%2)\n"
1677 " dins %0, %1, 16, 8\n"
1678 " andi %1, %2, 0x7\n"
1679 " beq $0, %1, 9f\n"
1680 " daddiu %2, %2, -1\n"
1681 "4: lb %1, 0(%2)\n"
1682 " dins %0, %1, 24, 8\n"
1683 " andi %1, %2, 0x7\n"
1684 " beq $0, %1, 9f\n"
1685 " daddiu %2, %2, -1\n"
1686 "5: lb %1, 0(%2)\n"
1687 " dinsu %0, %1, 32, 8\n"
1688 " andi %1, %2, 0x7\n"
1689 " beq $0, %1, 9f\n"
1690 " daddiu %2, %2, -1\n"
1691 "6: lb %1, 0(%2)\n"
1692 " dinsu %0, %1, 40, 8\n"
1693 " andi %1, %2, 0x7\n"
1694 " beq $0, %1, 9f\n"
1695 " daddiu %2, %2, -1\n"
1696 "7: lb %1, 0(%2)\n"
1697 " dinsu %0, %1, 48, 8\n"
1698 " andi %1, %2, 0x7\n"
1699 " beq $0, %1, 9f\n"
1700 " daddiu %2, %2, -1\n"
1701 "0: lb %1, 0(%2)\n"
1702 " dinsu %0, %1, 56, 8\n"
1704 "9:\n"
1705 " .insn\n"
1706 " .section .fixup,\"ax\"\n"
1707 "8: li %3,%4\n"
1708 " j 9b\n"
1709 " .previous\n"
1710 " .section __ex_table,\"a\"\n"
1711 STR(PTR_WD) " 1b,8b\n"
1712 STR(PTR_WD) " 2b,8b\n"
1713 STR(PTR_WD) " 3b,8b\n"
1714 STR(PTR_WD) " 4b,8b\n"
1715 STR(PTR_WD) " 5b,8b\n"
1716 STR(PTR_WD) " 6b,8b\n"
1717 STR(PTR_WD) " 7b,8b\n"
1718 STR(PTR_WD) " 0b,8b\n"
1719 " .previous\n"
1720 " .set pop\n"
1725 regs->regs[MIPSInst_RT(inst)] = rt;
1736 rt = regs->regs[MIPSInst_RT(inst)];
1737 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1739 current->thread.cp0_baduaddr = vaddr;
1744 " .set push\n"
1745 " .set reorder\n"
1747 " dextu %1, %0, 56, 8\n"
1748 "1: sb %1, 0(%2)\n"
1749 " andi %1, %2, 0x7\n"
1750 " beq $0, %1, 9f\n"
1751 " daddiu %2, %2, -1\n"
1752 " dextu %1, %0, 48, 8\n"
1753 "2: sb %1, 0(%2)\n"
1754 " andi %1, %2, 0x7\n"
1755 " beq $0, %1, 9f\n"
1756 " daddiu %2, %2, -1\n"
1757 " dextu %1, %0, 40, 8\n"
1758 "3: sb %1, 0(%2)\n"
1759 " andi %1, %2, 0x7\n"
1760 " beq $0, %1, 9f\n"
1761 " daddiu %2, %2, -1\n"
1762 " dextu %1, %0, 32, 8\n"
1763 "4: sb %1, 0(%2)\n"
1764 " andi %1, %2, 0x7\n"
1765 " beq $0, %1, 9f\n"
1766 " daddiu %2, %2, -1\n"
1767 " dext %1, %0, 24, 8\n"
1768 "5: sb %1, 0(%2)\n"
1769 " andi %1, %2, 0x7\n"
1770 " beq $0, %1, 9f\n"
1771 " daddiu %2, %2, -1\n"
1772 " dext %1, %0, 16, 8\n"
1773 "6: sb %1, 0(%2)\n"
1774 " andi %1, %2, 0x7\n"
1775 " beq $0, %1, 9f\n"
1776 " daddiu %2, %2, -1\n"
1777 " dext %1, %0, 8, 8\n"
1778 "7: sb %1, 0(%2)\n"
1779 " andi %1, %2, 0x7\n"
1780 " beq $0, %1, 9f\n"
1781 " daddiu %2, %2, -1\n"
1782 " dext %1, %0, 0, 8\n"
1783 "0: sb %1, 0(%2)\n"
1785 " dextu %1, %0, 56, 8\n"
1786 "1: sb %1, 0(%2)\n"
1787 " daddiu %2, %2, 1\n"
1788 " andi %1, %2, 0x7\n"
1789 " beq $0, %1, 9f\n"
1790 " dextu %1, %0, 48, 8\n"
1791 "2: sb %1, 0(%2)\n"
1792 " daddiu %2, %2, 1\n"
1793 " andi %1, %2, 0x7\n"
1794 " beq $0, %1, 9f\n"
1795 " dextu %1, %0, 40, 8\n"
1796 "3: sb %1, 0(%2)\n"
1797 " daddiu %2, %2, 1\n"
1798 " andi %1, %2, 0x7\n"
1799 " beq $0, %1, 9f\n"
1800 " dextu %1, %0, 32, 8\n"
1801 "4: sb %1, 0(%2)\n"
1802 " daddiu %2, %2, 1\n"
1803 " andi %1, %2, 0x7\n"
1804 " beq $0, %1, 9f\n"
1805 " dext %1, %0, 24, 8\n"
1806 "5: sb %1, 0(%2)\n"
1807 " daddiu %2, %2, 1\n"
1808 " andi %1, %2, 0x7\n"
1809 " beq $0, %1, 9f\n"
1810 " dext %1, %0, 16, 8\n"
1811 "6: sb %1, 0(%2)\n"
1812 " daddiu %2, %2, 1\n"
1813 " andi %1, %2, 0x7\n"
1814 " beq $0, %1, 9f\n"
1815 " dext %1, %0, 8, 8\n"
1816 "7: sb %1, 0(%2)\n"
1817 " daddiu %2, %2, 1\n"
1818 " andi %1, %2, 0x7\n"
1819 " beq $0, %1, 9f\n"
1820 " dext %1, %0, 0, 8\n"
1821 "0: sb %1, 0(%2)\n"
1823 "9:\n"
1824 " .insn\n"
1825 " .section .fixup,\"ax\"\n"
1826 "8: li %3,%4\n"
1827 " j 9b\n"
1828 " .previous\n"
1829 " .section __ex_table,\"a\"\n"
1830 STR(PTR_WD) " 1b,8b\n"
1831 STR(PTR_WD) " 2b,8b\n"
1832 STR(PTR_WD) " 3b,8b\n"
1833 STR(PTR_WD) " 4b,8b\n"
1834 STR(PTR_WD) " 5b,8b\n"
1835 STR(PTR_WD) " 6b,8b\n"
1836 STR(PTR_WD) " 7b,8b\n"
1837 STR(PTR_WD) " 0b,8b\n"
1838 " .previous\n"
1839 " .set pop\n"
1854 rt = regs->regs[MIPSInst_RT(inst)];
1855 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1857 current->thread.cp0_baduaddr = vaddr;
1862 " .set push\n"
1863 " .set reorder\n"
1865 " dext %1, %0, 0, 8\n"
1866 "1: sb %1, 0(%2)\n"
1867 " daddiu %2, %2, 1\n"
1868 " andi %1, %2, 0x7\n"
1869 " beq $0, %1, 9f\n"
1870 " dext %1, %0, 8, 8\n"
1871 "2: sb %1, 0(%2)\n"
1872 " daddiu %2, %2, 1\n"
1873 " andi %1, %2, 0x7\n"
1874 " beq $0, %1, 9f\n"
1875 " dext %1, %0, 16, 8\n"
1876 "3: sb %1, 0(%2)\n"
1877 " daddiu %2, %2, 1\n"
1878 " andi %1, %2, 0x7\n"
1879 " beq $0, %1, 9f\n"
1880 " dext %1, %0, 24, 8\n"
1881 "4: sb %1, 0(%2)\n"
1882 " daddiu %2, %2, 1\n"
1883 " andi %1, %2, 0x7\n"
1884 " beq $0, %1, 9f\n"
1885 " dextu %1, %0, 32, 8\n"
1886 "5: sb %1, 0(%2)\n"
1887 " daddiu %2, %2, 1\n"
1888 " andi %1, %2, 0x7\n"
1889 " beq $0, %1, 9f\n"
1890 " dextu %1, %0, 40, 8\n"
1891 "6: sb %1, 0(%2)\n"
1892 " daddiu %2, %2, 1\n"
1893 " andi %1, %2, 0x7\n"
1894 " beq $0, %1, 9f\n"
1895 " dextu %1, %0, 48, 8\n"
1896 "7: sb %1, 0(%2)\n"
1897 " daddiu %2, %2, 1\n"
1898 " andi %1, %2, 0x7\n"
1899 " beq $0, %1, 9f\n"
1900 " dextu %1, %0, 56, 8\n"
1901 "0: sb %1, 0(%2)\n"
1903 " dext %1, %0, 0, 8\n"
1904 "1: sb %1, 0(%2)\n"
1905 " andi %1, %2, 0x7\n"
1906 " beq $0, %1, 9f\n"
1907 " daddiu %2, %2, -1\n"
1908 " dext %1, %0, 8, 8\n"
1909 "2: sb %1, 0(%2)\n"
1910 " andi %1, %2, 0x7\n"
1911 " beq $0, %1, 9f\n"
1912 " daddiu %2, %2, -1\n"
1913 " dext %1, %0, 16, 8\n"
1914 "3: sb %1, 0(%2)\n"
1915 " andi %1, %2, 0x7\n"
1916 " beq $0, %1, 9f\n"
1917 " daddiu %2, %2, -1\n"
1918 " dext %1, %0, 24, 8\n"
1919 "4: sb %1, 0(%2)\n"
1920 " andi %1, %2, 0x7\n"
1921 " beq $0, %1, 9f\n"
1922 " daddiu %2, %2, -1\n"
1923 " dextu %1, %0, 32, 8\n"
1924 "5: sb %1, 0(%2)\n"
1925 " andi %1, %2, 0x7\n"
1926 " beq $0, %1, 9f\n"
1927 " daddiu %2, %2, -1\n"
1928 " dextu %1, %0, 40, 8\n"
1929 "6: sb %1, 0(%2)\n"
1930 " andi %1, %2, 0x7\n"
1931 " beq $0, %1, 9f\n"
1932 " daddiu %2, %2, -1\n"
1933 " dextu %1, %0, 48, 8\n"
1934 "7: sb %1, 0(%2)\n"
1935 " andi %1, %2, 0x7\n"
1936 " beq $0, %1, 9f\n"
1937 " daddiu %2, %2, -1\n"
1938 " dextu %1, %0, 56, 8\n"
1939 "0: sb %1, 0(%2)\n"
1941 "9:\n"
1942 " .insn\n"
1943 " .section .fixup,\"ax\"\n"
1944 "8: li %3,%4\n"
1945 " j 9b\n"
1946 " .previous\n"
1947 " .section __ex_table,\"a\"\n"
1948 STR(PTR_WD) " 1b,8b\n"
1949 STR(PTR_WD) " 2b,8b\n"
1950 STR(PTR_WD) " 3b,8b\n"
1951 STR(PTR_WD) " 4b,8b\n"
1952 STR(PTR_WD) " 5b,8b\n"
1953 STR(PTR_WD) " 6b,8b\n"
1954 STR(PTR_WD) " 7b,8b\n"
1955 STR(PTR_WD) " 0b,8b\n"
1956 " .previous\n"
1957 " .set pop\n"
1967 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1969 current->thread.cp0_baduaddr = vaddr;
1974 current->thread.cp0_baduaddr = vaddr;
1994 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
2000 "1:\n"
2001 "ll %0, 0(%2)\n"
2002 "2:\n"
2003 ".insn\n"
2004 ".section .fixup,\"ax\"\n"
2005 "3:\n"
2006 "li %1, %3\n"
2007 "j 2b\n"
2008 ".previous\n"
2009 ".section __ex_table,\"a\"\n"
2010 STR(PTR_WD) " 1b,3b\n"
2011 ".previous\n"
2017 regs->regs[MIPSInst_RT(inst)] = res;
2023 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
2025 current->thread.cp0_baduaddr = vaddr;
2030 current->thread.cp0_baduaddr = vaddr;
2050 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
2055 res = regs->regs[MIPSInst_RT(inst)];
2058 "1:\n"
2059 "sc %0, 0(%2)\n"
2060 "2:\n"
2061 ".insn\n"
2062 ".section .fixup,\"ax\"\n"
2063 "3:\n"
2064 "li %1, %3\n"
2065 "j 2b\n"
2066 ".previous\n"
2067 ".section __ex_table,\"a\"\n"
2068 STR(PTR_WD) " 1b,3b\n"
2069 ".previous\n"
2074 regs->regs[MIPSInst_RT(inst)] = res;
2086 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
2088 current->thread.cp0_baduaddr = vaddr;
2093 current->thread.cp0_baduaddr = vaddr;
2113 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
2119 "1:\n"
2120 "lld %0, 0(%2)\n"
2121 "2:\n"
2122 ".insn\n"
2123 ".section .fixup,\"ax\"\n"
2124 "3:\n"
2125 "li %1, %3\n"
2126 "j 2b\n"
2127 ".previous\n"
2128 ".section __ex_table,\"a\"\n"
2129 STR(PTR_WD) " 1b,3b\n"
2130 ".previous\n"
2135 regs->regs[MIPSInst_RT(inst)] = res;
2147 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
2149 current->thread.cp0_baduaddr = vaddr;
2154 current->thread.cp0_baduaddr = vaddr;
2174 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
2179 res = regs->regs[MIPSInst_RT(inst)];
2182 "1:\n"
2183 "scd %0, 0(%2)\n"
2184 "2:\n"
2185 ".insn\n"
2186 ".section .fixup,\"ax\"\n"
2187 "3:\n"
2188 "li %1, %3\n"
2189 "j 2b\n"
2190 ".previous\n"
2191 ".section __ex_table,\"a\"\n"
2192 STR(PTR_WD) " 1b,3b\n"
2193 ".previous\n"
2198 regs->regs[MIPSInst_RT(inst)] = res;
2215 regs->cp0_cause &= ~CAUSEF_BD;
2216 err = get_user(inst, (u32 __user *)regs->cp0_epc);
2225 regs->regs[31] = r31;
2226 regs->cp0_epc = epc;
2241 seq_printf(s, "Instruction\tTotal\tBDslot\n------------------------------\n");
2242 seq_printf(s, "movs\t\t%ld\t%ld\n",
2245 seq_printf(s, "hilo\t\t%ld\t%ld\n",
2248 seq_printf(s, "muls\t\t%ld\t%ld\n",
2251 seq_printf(s, "divs\t\t%ld\t%ld\n",
2254 seq_printf(s, "dsps\t\t%ld\t%ld\n",
2257 seq_printf(s, "bops\t\t%ld\t%ld\n",
2260 seq_printf(s, "traps\t\t%ld\t%ld\n",
2263 seq_printf(s, "fpus\t\t%ld\t%ld\n",
2266 seq_printf(s, "loads\t\t%ld\t%ld\n",
2269 seq_printf(s, "stores\t\t%ld\t%ld\n",
2272 seq_printf(s, "llsc\t\t%ld\t%ld\n",
2275 seq_printf(s, "dsemul\t\t%ld\t%ld\n",
2278 seq_printf(s, "jr\t\t%ld\n",
2280 seq_printf(s, "bltzl\t\t%ld\n",
2282 seq_printf(s, "bgezl\t\t%ld\n",
2284 seq_printf(s, "bltzll\t\t%ld\n",
2286 seq_printf(s, "bgezll\t\t%ld\n",
2288 seq_printf(s, "bltzal\t\t%ld\n",
2290 seq_printf(s, "bgezal\t\t%ld\n",
2292 seq_printf(s, "beql\t\t%ld\n",
2294 seq_printf(s, "bnel\t\t%ld\n",
2296 seq_printf(s, "blezl\t\t%ld\n",
2298 seq_printf(s, "bgtzl\t\t%ld\n",