mips/ath79/clock.c

105 	pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
131 	pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
165 	clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
178 		cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG);
253 	pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
257 		pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
265 		pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG);
280 	pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
284 		pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
292 		pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG);
307 	clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
343 	clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
368 	pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
382 	pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG);
396 	clk_ctrl = __raw_readl(pll_base + QCA953X_PLL_CLK_CTRL_REG);
451 	pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
465 	pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG);
479 	clk_ctrl = __raw_readl(pll_base + QCA955X_PLL_CLK_CTRL_REG);
544 	pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
550 	pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG);
563 	pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG);
568 	pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG);
581 	clk_ctrl = __raw_readl(pll_base + QCA956X_PLL_CLK_CTRL_REG);