Lines Matching defs:lr_val
555 u64 *lr_val)
583 *lr_val = val;
588 *lr_val = ICC_IAR1_EL1_SPURIOUS;
594 u64 *lr_val)
604 *lr_val = val;
609 *lr_val = ICC_IAR1_EL1_SPURIOUS;
746 u64 lr_val;
752 lr = __vgic_v3_highest_priority_lr(vcpu, vmcr, &lr_val);
756 if (grp != !!(lr_val & ICH_LR_GROUP))
760 lr_prio = (lr_val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT;
767 lr_val &= ~ICH_LR_STATE;
768 lr_val |= ICH_LR_ACTIVE_BIT;
769 __gic_v3_set_lr(lr_val, lr);
771 vcpu_set_reg(vcpu, rt, lr_val & ICH_LR_VIRTUAL_ID_MASK);
778 static void __vgic_v3_clear_active_lr(int lr, u64 lr_val)
780 lr_val &= ~ICH_LR_ACTIVE_BIT;
781 if (lr_val & ICH_LR_HW) {
784 pid = (lr_val & ICH_LR_PHYS_ID_MASK) >> ICH_LR_PHYS_ID_SHIFT;
788 __gic_v3_set_lr(lr_val, lr);
803 u64 lr_val;
814 lr = __vgic_v3_find_active_lr(vcpu, vid, &lr_val);
820 __vgic_v3_clear_active_lr(lr, lr_val);
826 u64 lr_val;
835 lr = __vgic_v3_find_active_lr(vcpu, vid, &lr_val);
847 lr_prio = (lr_val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT;
850 if (grp != !!(lr_val & ICH_LR_GROUP) ||
855 __vgic_v3_clear_active_lr(lr, lr_val);
1005 u64 lr_val;
1010 lr = __vgic_v3_highest_priority_lr(vcpu, vmcr, &lr_val);
1014 lr_grp = !!(lr_val & ICH_LR_GROUP);
1016 lr_val = ICC_IAR1_EL1_SPURIOUS;
1019 vcpu_set_reg(vcpu, rt, lr_val & ICH_LR_VIRTUAL_ID_MASK);