Lines Matching +full:2 +full:- +full:3
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
17 #include <asm/gpr-num.h>
22 * C5.2, version:ARM DDI 0487A.f)
23 * [20-19] : Op0
24 * [18-16] : Op1
25 * [15-12] : CRn
26 * [11-8] : CRm
27 * [7-5] : Op2
84 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
97 #define PSTATE_UAO pstate_field(0, 3)
98 #define PSTATE_SSBS pstate_field(3, 1)
99 #define PSTATE_DIT pstate_field(3, 2)
100 #define PSTATE_TCO pstate_field(3, 4)
113 /* Register-based PAN access, for save/restore purposes */
114 #define SYS_PSTATE_PAN sys_reg(3, 0, 4, 2, 3)
121 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 3, 3, 0, 7, 31)
126 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
129 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
132 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
138 #define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1)
141 #define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3)
144 #define SYS_DC_CVAC sys_insn(1, 3, 7, 10, 1)
145 #define SYS_DC_CGVAC sys_insn(1, 3, 7, 10, 3)
146 #define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5)
148 #define SYS_DC_CVAU sys_insn(1, 3, 7, 11, 1)
150 #define SYS_DC_CVAP sys_insn(1, 3, 7, 12, 1)
151 #define SYS_DC_CGVAP sys_insn(1, 3, 7, 12, 3)
152 #define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5)
154 #define SYS_DC_CVADP sys_insn(1, 3, 7, 13, 1)
155 #define SYS_DC_CGVADP sys_insn(1, 3, 7, 13, 3)
156 #define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5)
158 #define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1)
159 #define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3)
160 #define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5)
162 #define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1)
163 #define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3)
164 #define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4)
175 #include "asm/sysreg-defs.h"
181 #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3)
182 #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3)
183 #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3)
185 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
186 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
187 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
188 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
189 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
191 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
192 #define OSLSR_EL1_OSLM_MASK (BIT(3) | BIT(0))
194 #define OSLSR_EL1_OSLM_IMPLEMENTED BIT(3)
197 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
198 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
199 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
200 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
201 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
202 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
203 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
204 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
205 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
206 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
208 #define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
209 #define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
210 #define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
212 #define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
213 #define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
214 #define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
215 #define SYS_TRCAUTHSTATUS sys_reg(2, 1, 7, 14, 6)
216 #define SYS_TRCAUXCTLR sys_reg(2, 1, 0, 6, 0)
217 #define SYS_TRCBBCTLR sys_reg(2, 1, 0, 15, 0)
218 #define SYS_TRCCCCTLR sys_reg(2, 1, 0, 14, 0)
219 #define SYS_TRCCIDCCTLR0 sys_reg(2, 1, 3, 0, 2)
220 #define SYS_TRCCIDCCTLR1 sys_reg(2, 1, 3, 1, 2)
221 #define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0)
222 #define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6)
223 #define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6)
224 #define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5)
225 #define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5)
226 #define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
227 #define SYS_TRCCONFIGR sys_reg(2, 1, 0, 4, 0)
228 #define SYS_TRCDEVARCH sys_reg(2, 1, 7, 15, 6)
229 #define SYS_TRCDEVID sys_reg(2, 1, 7, 2, 7)
230 #define SYS_TRCEVENTCTL0R sys_reg(2, 1, 0, 8, 0)
231 #define SYS_TRCEVENTCTL1R sys_reg(2, 1, 0, 9, 0)
232 #define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4)
233 #define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7)
234 #define SYS_TRCIDR10 sys_reg(2, 1, 0, 2, 6)
235 #define SYS_TRCIDR11 sys_reg(2, 1, 0, 3, 6)
236 #define SYS_TRCIDR12 sys_reg(2, 1, 0, 4, 6)
237 #define SYS_TRCIDR13 sys_reg(2, 1, 0, 5, 6)
238 #define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
239 #define SYS_TRCIDR2 sys_reg(2, 1, 0, 10, 7)
240 #define SYS_TRCIDR3 sys_reg(2, 1, 0, 11, 7)
241 #define SYS_TRCIDR4 sys_reg(2, 1, 0, 12, 7)
242 #define SYS_TRCIDR5 sys_reg(2, 1, 0, 13, 7)
243 #define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7)
244 #define SYS_TRCIDR7 sys_reg(2, 1, 0, 15, 7)
245 #define SYS_TRCIDR8 sys_reg(2, 1, 0, 0, 6)
246 #define SYS_TRCIDR9 sys_reg(2, 1, 0, 1, 6)
247 #define SYS_TRCIMSPEC(m) sys_reg(2, 1, 0, (m & 7), 7)
248 #define SYS_TRCITEEDCR sys_reg(2, 1, 0, 2, 1)
249 #define SYS_TRCOSLSR sys_reg(2, 1, 1, 1, 4)
250 #define SYS_TRCPRGCTLR sys_reg(2, 1, 0, 1, 0)
251 #define SYS_TRCQCTLR sys_reg(2, 1, 0, 1, 1)
252 #define SYS_TRCRSCTLR(m) sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4)))
253 #define SYS_TRCRSR sys_reg(2, 1, 0, 10, 0)
254 #define SYS_TRCSEQEVR(m) sys_reg(2, 1, 0, (m & 3), 4)
255 #define SYS_TRCSEQRSTEVR sys_reg(2, 1, 0, 6, 4)
256 #define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4)
257 #define SYS_TRCSSCCR(m) sys_reg(2, 1, 1, (m & 7), 2)
258 #define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2)
259 #define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3)
260 #define SYS_TRCSTALLCTLR sys_reg(2, 1, 0, 11, 0)
261 #define SYS_TRCSTATR sys_reg(2, 1, 0, 3, 0)
262 #define SYS_TRCSYNCPR sys_reg(2, 1, 0, 13, 0)
263 #define SYS_TRCTRACEIDR sys_reg(2, 1, 0, 0, 1)
264 #define SYS_TRCTSCTLR sys_reg(2, 1, 0, 12, 0)
265 #define SYS_TRCVICTLR sys_reg(2, 1, 0, 0, 2)
266 #define SYS_TRCVIIECTLR sys_reg(2, 1, 0, 1, 2)
267 #define SYS_TRCVIPCSSCTLR sys_reg(2, 1, 0, 3, 2)
268 #define SYS_TRCVISSCTLR sys_reg(2, 1, 0, 2, 2)
269 #define SYS_TRCVMIDCCTLR0 sys_reg(2, 1, 3, 2, 2)
270 #define SYS_TRCVMIDCCTLR1 sys_reg(2, 1, 3, 3, 2)
271 #define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1)
274 #define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4)
276 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
277 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
278 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
280 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
281 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
282 #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
284 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
286 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
287 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
288 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
289 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3)
291 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0)
292 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1)
293 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2)
294 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3)
296 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0)
297 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
299 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
300 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
302 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
304 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
305 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
306 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
308 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
309 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
310 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
311 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
312 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
313 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
314 #define SYS_ERXPFGF_EL1 sys_reg(3, 0, 5, 4, 4)
315 #define SYS_ERXPFGCTL_EL1 sys_reg(3, 0, 5, 4, 5)
316 #define SYS_ERXPFGCDN_EL1 sys_reg(3, 0, 5, 4, 6)
317 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
318 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
319 #define SYS_ERXMISC2_EL1 sys_reg(3, 0, 5, 5, 2)
320 #define SYS_ERXMISC3_EL1 sys_reg(3, 0, 5, 5, 3)
321 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
322 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
324 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
350 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
370 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
371 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
373 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
375 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
376 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
378 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
379 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
381 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
382 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
383 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
384 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
385 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
388 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2)
389 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3)
390 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
393 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2)
394 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3)
395 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
396 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
397 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
398 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
399 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
400 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
401 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
402 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
403 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
404 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
405 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
406 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
407 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
409 #define SYS_ACCDATA_EL1 sys_reg(3, 0, 13, 0, 5)
411 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
413 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
415 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
416 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
418 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
419 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
420 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
421 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
422 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
423 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
424 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
425 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
426 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
427 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
428 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
429 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
431 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
432 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
433 #define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5)
435 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
438 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2))
439 #define SYS_AMCR_EL0 SYS_AM_EL0(2, 0)
440 #define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1)
441 #define SYS_AMCGCR_EL0 SYS_AM_EL0(2, 2)
442 #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3)
443 #define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4)
444 #define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5)
445 #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0)
446 #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1)
451 * Counter: 11 011 1101 010:n<3> n<2:0>
452 * Type: 11 011 1101 011:n<3> n<2:0>
453 * n: 0-15
457 * Counter: 11 011 1101 110:n<3> n<2:0>
458 * Type: 11 011 1101 111:n<3> n<2:0>
459 * n: 0-15
462 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
463 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
464 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
465 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
470 #define SYS_AMEVCNTR0_INST_RET_EL0 SYS_AMEVCNTR0_EL0(2)
471 #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3)
473 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
475 #define SYS_CNTPCT_EL0 sys_reg(3, 3, 14, 0, 1)
476 #define SYS_CNTVCT_EL0 sys_reg(3, 3, 14, 0, 2)
477 #define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5)
478 #define SYS_CNTVCTSS_EL0 sys_reg(3, 3, 14, 0, 6)
480 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
481 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
482 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
484 #define SYS_CNTV_TVAL_EL0 sys_reg(3, 3, 14, 3, 0)
485 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1)
486 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2)
488 #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0)
489 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1)
492 #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0)
497 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
498 #define SYS_PMEVCNTSVRn_EL1(n) sys_reg(2, 0, 14, __CNTR_CRm(n), __PMEV_op2(n))
499 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
500 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
501 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
503 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
505 #define SYS_SPMCGCRn_EL1(n) sys_reg(2, 0, 9, 13, ((n) & 1))
508 #define __SPMEV_crm(p, n) ((((p) & 7) << 1) | (((n) >> 3) & 1))
509 #define SYS_SPMEVCNTRn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b000, n), __SPMEV_op2(n))
510 #define SYS_SPMEVFILT2Rn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b011, n), __SPMEV_op2(n))
511 #define SYS_SPMEVFILTRn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b010, n), __SPMEV_op2(n))
512 #define SYS_SPMEVTYPERn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b001, n), __SPMEV_op2(n))
514 #define SYS_VPIDR_EL2 sys_reg(3, 4, 0, 0, 0)
515 #define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5)
517 #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
518 #define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1)
519 #define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3)
520 #define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0)
521 #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
522 #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
523 #define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)
524 #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
526 #define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0)
527 #define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1)
528 #define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2)
529 #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
530 #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
532 #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
533 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
534 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
535 #define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0)
536 #define SYS_SPSR_irq sys_reg(3, 4, 4, 3, 0)
537 #define SYS_SPSR_abt sys_reg(3, 4, 4, 3, 1)
538 #define SYS_SPSR_und sys_reg(3, 4, 4, 3, 2)
539 #define SYS_SPSR_fiq sys_reg(3, 4, 4, 3, 3)
540 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
541 #define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
542 #define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
543 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
544 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
545 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
546 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
548 #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
549 #define SYS_HPFAR_EL2 sys_reg(3, 4, 6, 0, 4)
551 #define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0)
552 #define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0)
554 #define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0)
555 #define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1)
556 #define SYS_RMR_EL2 sys_reg(3, 4, 12, 0, 2)
557 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
558 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
561 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2)
562 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
564 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
567 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2)
568 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
570 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
571 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
572 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
573 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
574 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
576 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
579 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2)
580 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
586 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
589 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2)
590 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
596 #define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1)
597 #define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2)
598 #define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7)
601 #define __AMEV_CRm(n, m) (n | ((m & 0x8) >> 3))
602 #define __SYS__AMEVCNTVOFF0n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m))
604 #define __SYS__AMEVCNTVOFF1n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m))
607 #define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3)
608 #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0)
609 #define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0)
610 #define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1)
611 #define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2)
612 #define SYS_CNTHV_TVAL_EL2 sys_reg(3, 4, 14, 3, 0)
613 #define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1)
614 #define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2)
617 #define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)
618 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
619 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
620 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
621 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
622 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
623 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
624 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
625 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
626 #define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0)
627 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
628 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
629 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
630 #define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7)
631 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
632 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
633 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
634 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
635 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
636 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
637 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
639 #define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0)
647 #define OP_AT_S1E0R sys_insn(AT_Op0, 0, AT_CRn, 8, 2)
648 #define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
651 #define OP_AT_S1E1A sys_insn(AT_Op0, 0, AT_CRn, 9, 2)
658 #define OP_AT_S1E2A sys_insn(AT_Op0, 4, AT_CRn, 9, 2)
669 #define TLBI_CRm_IPAIS 0 /* S2 Inner-Shareable */
670 #define TLBI_CRm_nROS 1 /* non-Range, Outer-Sharable */
671 #define TLBI_CRm_RIS 2 /* Range, Inner-Sharable */
672 #define TLBI_CRm_nRIS 3 /* non-Range, Inner-Sharable */
673 #define TLBI_CRm_IPAONS 4 /* S2 Outer and Non-Shareable */
674 #define TLBI_CRm_ROS 5 /* Range, Outer-Sharable */
675 #define TLBI_CRm_RNS 6 /* Range, Non-Sharable */
676 #define TLBI_CRm_nRNS 7 /* non-Range, Non-Sharable */
680 #define OP_TLBI_ASIDE1OS sys_insn(1, 0, 8, 1, 2)
681 #define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3)
684 #define OP_TLBI_RVAE1IS sys_insn(1, 0, 8, 2, 1)
685 #define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3)
686 #define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5)
687 #define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7)
688 #define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0)
689 #define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1)
690 #define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2)
691 #define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3)
692 #define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)
693 #define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
695 #define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)
699 #define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3)
704 #define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2)
705 #define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
710 #define OP_TLBI_ASIDE1OSNXS sys_insn(1, 0, 9, 1, 2)
711 #define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3)
714 #define OP_TLBI_RVAE1ISNXS sys_insn(1, 0, 9, 2, 1)
715 #define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3)
716 #define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
717 #define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)
718 #define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0)
719 #define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1)
720 #define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2)
721 #define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3)
722 #define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
723 #define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
725 #define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
729 #define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3)
734 #define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)
735 #define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
739 #define OP_TLBI_RIPAS2E1IS sys_insn(1, 4, 8, 0, 2)
747 #define OP_TLBI_RVAE2IS sys_insn(1, 4, 8, 2, 1)
748 #define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5)
749 #define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0)
750 #define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1)
751 #define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4)
752 #define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
753 #define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6)
756 #define OP_TLBI_RIPAS2E1 sys_insn(1, 4, 8, 4, 2)
757 #define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3)
772 #define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2)
780 #define OP_TLBI_RVAE2ISNXS sys_insn(1, 4, 9, 2, 1)
781 #define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
782 #define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0)
783 #define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1)
784 #define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4)
785 #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
786 #define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6)
789 #define OP_TLBI_RIPAS2E1NXS sys_insn(1, 4, 9, 4, 2)
790 #define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3)
809 #define OP_GCSPUSHM sys_insn(1, 3, 7, 7, 0)
811 #define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4)
812 #define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5)
813 #define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4)
814 #define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
815 #define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6)
816 #define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
846 #define SCTLR_ELx_SA (BIT(3))
847 #define SCTLR_ELx_C (BIT(2))
961 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
989 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
994 #define ICH_LR_STATE (3ULL << 62)
1003 #define ICH_VMCR_ACK_CTL_SHIFT 2
1005 #define ICH_VMCR_FIQ_EN_SHIFT 3
1084 #define GICV5_OP_GIC_CDAFF sys_insn(1, 0, 12, 1, 3)
1085 #define GICV5_OP_GIC_CDDI sys_insn(1, 0, 12, 2, 0)
1087 #define GICV5_OP_GIC_CDHM sys_insn(1, 0, 12, 2, 1)
1091 #define GICV5_OP_GIC_CDPRI sys_insn(1, 0, 12, 1, 2)
1093 #define GICV5_OP_GICR_CDIA sys_insn(1, 0, 12, 3, 0)
1245 * set mask are set. Other bits are left as-is.