Lines Matching +full:am3352 +full:- +full:ehrpwm
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
24 #size-cells = <1>;
27 atf-sram@0 {
31 tifs-sram@1f0000 {
35 l3cache-sram@200000 {
41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
43 #address-cells = <1>;
44 #size-cells = <1>;
47 usb_serdes_mux: mux-controller@0 {
48 compatible = "reg-mux";
50 #mux-control-cells = <1>;
51 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
55 compatible = "ti,am654-phy-gmii-sel";
57 #phy-cells = <1>;
60 pcie1_ctrl: pcie-ctrl@74 {
61 compatible = "ti,j784s4-pcie-ctrl", "syscon";
65 serdes_ln_ctrl: mux-controller@80 {
66 compatible = "reg-mux";
68 #mux-control-cells = <1>;
69 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
73 ehrpwm_tbclk: clock-controller@140 {
74 compatible = "ti,am654-ehrpwm-tbclk";
76 #clock-cells = <1>;
81 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
82 #pwm-cells = <3>;
84 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
86 clock-names = "tbclk", "fck";
91 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
92 #pwm-cells = <3>;
94 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
96 clock-names = "tbclk", "fck";
101 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
102 #pwm-cells = <3>;
104 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
106 clock-names = "tbclk", "fck";
111 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
112 #pwm-cells = <3>;
114 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
116 clock-names = "tbclk", "fck";
121 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
122 #pwm-cells = <3>;
124 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
126 clock-names = "tbclk", "fck";
131 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
132 #pwm-cells = <3>;
134 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
136 clock-names = "tbclk", "fck";
140 gic500: interrupt-controller@1800000 {
141 compatible = "arm,gic-v3";
142 #address-cells = <2>;
143 #size-cells = <2>;
145 #interrupt-cells = <3>;
146 interrupt-controller;
156 gic_its: msi-controller@1820000 {
157 compatible = "arm,gic-v3-its";
159 socionext,synquacer-pre-its = <0x1000000 0x400000>;
160 msi-controller;
161 #msi-cells = <1>;
165 main_gpio_intr: interrupt-controller@a00000 {
166 compatible = "ti,sci-intr";
168 ti,intr-trigger-type = <1>;
169 interrupt-controller;
170 interrupt-parent = <&gic500>;
171 #interrupt-cells = <1>;
173 ti,sci-dev-id = <148>;
174 ti,interrupt-ranges = <8 392 56>;
178 compatible = "pinctrl-single";
181 #pinctrl-cells = <1>;
182 pinctrl-single,register-width = <32>;
183 pinctrl-single,function-mask = <0xffffffff>;
188 compatible = "pinctrl-single";
190 #pinctrl-cells = <1>;
191 pinctrl-single,register-width = <32>;
192 pinctrl-single,function-mask = <0x00000007>;
197 compatible = "pinctrl-single";
199 #pinctrl-cells = <1>;
200 pinctrl-single,register-width = <32>;
201 pinctrl-single,function-mask = <0x0000001f>;
205 compatible = "ti,j721e-sa2ul";
207 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
208 #address-cells = <2>;
209 #size-cells = <2>;
214 dma-names = "tx", "rx1", "rx2";
217 compatible = "inside-secure,safexcel-eip76";
224 compatible = "ti,am654-timer";
228 clock-names = "fck";
229 assigned-clocks = <&k3_clks 63 1>;
230 assigned-clock-parents = <&k3_clks 63 2>;
231 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
232 ti,timer-pwm;
236 compatible = "ti,am654-timer";
240 clock-names = "fck";
241 assigned-clocks = <&k3_clks 64 1>;
242 assigned-clock-parents = <&k3_clks 64 2>;
243 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
244 ti,timer-pwm;
248 compatible = "ti,am654-timer";
252 clock-names = "fck";
253 assigned-clocks = <&k3_clks 65 1>;
254 assigned-clock-parents = <&k3_clks 65 2>;
255 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
256 ti,timer-pwm;
260 compatible = "ti,am654-timer";
264 clock-names = "fck";
265 assigned-clocks = <&k3_clks 66 1>;
266 assigned-clock-parents = <&k3_clks 66 2>;
267 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
268 ti,timer-pwm;
272 compatible = "ti,am654-timer";
276 clock-names = "fck";
277 assigned-clocks = <&k3_clks 67 1>;
278 assigned-clock-parents = <&k3_clks 67 2>;
279 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
280 ti,timer-pwm;
284 compatible = "ti,am654-timer";
288 clock-names = "fck";
289 assigned-clocks = <&k3_clks 68 1>;
290 assigned-clock-parents = <&k3_clks 68 2>;
291 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
292 ti,timer-pwm;
296 compatible = "ti,am654-timer";
300 clock-names = "fck";
301 assigned-clocks = <&k3_clks 69 1>;
302 assigned-clock-parents = <&k3_clks 69 2>;
303 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
304 ti,timer-pwm;
308 compatible = "ti,am654-timer";
312 clock-names = "fck";
313 assigned-clocks = <&k3_clks 70 1>;
314 assigned-clock-parents = <&k3_clks 70 2>;
315 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
316 ti,timer-pwm;
320 compatible = "ti,am654-timer";
324 clock-names = "fck";
325 assigned-clocks = <&k3_clks 71 1>;
326 assigned-clock-parents = <&k3_clks 71 2>;
327 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
328 ti,timer-pwm;
332 compatible = "ti,am654-timer";
336 clock-names = "fck";
337 assigned-clocks = <&k3_clks 72 1>;
338 assigned-clock-parents = <&k3_clks 72 2>;
339 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
340 ti,timer-pwm;
344 compatible = "ti,am654-timer";
348 clock-names = "fck";
349 assigned-clocks = <&k3_clks 73 1>;
350 assigned-clock-parents = <&k3_clks 73 2>;
351 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
352 ti,timer-pwm;
356 compatible = "ti,am654-timer";
360 clock-names = "fck";
361 assigned-clocks = <&k3_clks 74 1>;
362 assigned-clock-parents = <&k3_clks 74 2>;
363 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
364 ti,timer-pwm;
368 compatible = "ti,am654-timer";
372 clock-names = "fck";
373 assigned-clocks = <&k3_clks 75 1>;
374 assigned-clock-parents = <&k3_clks 75 2>;
375 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
376 ti,timer-pwm;
380 compatible = "ti,am654-timer";
384 clock-names = "fck";
385 assigned-clocks = <&k3_clks 76 1>;
386 assigned-clock-parents = <&k3_clks 76 2>;
387 power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>;
388 ti,timer-pwm;
392 compatible = "ti,am654-timer";
396 clock-names = "fck";
397 assigned-clocks = <&k3_clks 77 1>;
398 assigned-clock-parents = <&k3_clks 77 2>;
399 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
400 ti,timer-pwm;
404 compatible = "ti,am654-timer";
408 clock-names = "fck";
409 assigned-clocks = <&k3_clks 78 1>;
410 assigned-clock-parents = <&k3_clks 78 2>;
411 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
412 ti,timer-pwm;
416 compatible = "ti,am654-timer";
420 clock-names = "fck";
421 assigned-clocks = <&k3_clks 79 1>;
422 assigned-clock-parents = <&k3_clks 79 2>;
423 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
424 ti,timer-pwm;
428 compatible = "ti,am654-timer";
432 clock-names = "fck";
433 assigned-clocks = <&k3_clks 80 1>;
434 assigned-clock-parents = <&k3_clks 80 2>;
435 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
436 ti,timer-pwm;
440 compatible = "ti,am654-timer";
444 clock-names = "fck";
445 assigned-clocks = <&k3_clks 81 1>;
446 assigned-clock-parents = <&k3_clks 81 2>;
447 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>;
448 ti,timer-pwm;
452 compatible = "ti,am654-timer";
456 clock-names = "fck";
457 assigned-clocks = <&k3_clks 82 1>;
458 assigned-clock-parents = <&k3_clks 82 2>;
459 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>;
460 ti,timer-pwm;
464 compatible = "ti,j721e-uart", "ti,am654-uart";
468 clock-names = "fclk";
469 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
474 compatible = "ti,j721e-uart", "ti,am654-uart";
478 clock-names = "fclk";
479 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
484 compatible = "ti,j721e-uart", "ti,am654-uart";
488 clock-names = "fclk";
489 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
494 compatible = "ti,j721e-uart", "ti,am654-uart";
498 clock-names = "fclk";
499 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
504 compatible = "ti,j721e-uart", "ti,am654-uart";
508 clock-names = "fclk";
509 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
514 compatible = "ti,j721e-uart", "ti,am654-uart";
518 clock-names = "fclk";
519 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
524 compatible = "ti,j721e-uart", "ti,am654-uart";
528 clock-names = "fclk";
529 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
534 compatible = "ti,j721e-uart", "ti,am654-uart";
538 clock-names = "fclk";
539 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
544 compatible = "ti,j721e-uart", "ti,am654-uart";
548 clock-names = "fclk";
549 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
554 compatible = "ti,j721e-uart", "ti,am654-uart";
558 clock-names = "fclk";
559 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
564 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
566 gpio-controller;
567 #gpio-cells = <2>;
568 interrupt-parent = <&main_gpio_intr>;
570 interrupt-controller;
571 #interrupt-cells = <2>;
573 ti,davinci-gpio-unbanked = <0>;
574 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
576 clock-names = "gpio";
581 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
583 gpio-controller;
584 #gpio-cells = <2>;
585 interrupt-parent = <&main_gpio_intr>;
587 interrupt-controller;
588 #interrupt-cells = <2>;
590 ti,davinci-gpio-unbanked = <0>;
591 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
593 clock-names = "gpio";
598 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
600 gpio-controller;
601 #gpio-cells = <2>;
602 interrupt-parent = <&main_gpio_intr>;
604 interrupt-controller;
605 #interrupt-cells = <2>;
607 ti,davinci-gpio-unbanked = <0>;
608 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
610 clock-names = "gpio";
615 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
617 gpio-controller;
618 #gpio-cells = <2>;
619 interrupt-parent = <&main_gpio_intr>;
621 interrupt-controller;
622 #interrupt-cells = <2>;
624 ti,davinci-gpio-unbanked = <0>;
625 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
627 clock-names = "gpio";
632 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
635 #address-cells = <1>;
636 #size-cells = <0>;
638 clock-names = "fck";
639 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
643 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
646 #address-cells = <1>;
647 #size-cells = <0>;
649 clock-names = "fck";
650 power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
655 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
658 #address-cells = <1>;
659 #size-cells = <0>;
661 clock-names = "fck";
662 power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
667 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
670 #address-cells = <1>;
671 #size-cells = <0>;
673 clock-names = "fck";
674 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
679 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
682 #address-cells = <1>;
683 #size-cells = <0>;
685 clock-names = "fck";
686 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
691 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
694 #address-cells = <1>;
695 #size-cells = <0>;
697 clock-names = "fck";
698 power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
703 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
706 #address-cells = <1>;
707 #size-cells = <0>;
709 clock-names = "fck";
710 power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
714 vpu: video-codec@4210000 {
715 compatible = "ti,j721s2-wave521c", "cnm,wave521c";
719 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
723 compatible = "ti,j721e-sdhci-8bit";
727 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
729 clock-names = "clk_ahb", "clk_xin";
730 assigned-clocks = <&k3_clks 98 1>;
731 assigned-clock-parents = <&k3_clks 98 2>;
732 bus-width = <8>;
733 ti,otap-del-sel-legacy = <0x0>;
734 ti,otap-del-sel-mmc-hs = <0x0>;
735 ti,otap-del-sel-ddr52 = <0x6>;
736 ti,otap-del-sel-hs200 = <0x8>;
737 ti,otap-del-sel-hs400 = <0x5>;
738 ti,itap-del-sel-legacy = <0x10>;
739 ti,itap-del-sel-mmc-hs = <0xa>;
740 ti,strobe-sel = <0x77>;
741 ti,clkbuf-sel = <0x7>;
742 ti,trm-icp = <0x8>;
743 mmc-ddr-1_8v;
744 mmc-hs200-1_8v;
745 mmc-hs400-1_8v;
746 dma-coherent;
751 compatible = "ti,j721e-sdhci-4bit";
755 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
757 clock-names = "clk_ahb", "clk_xin";
758 assigned-clocks = <&k3_clks 99 1>;
759 assigned-clock-parents = <&k3_clks 99 2>;
760 bus-width = <4>;
761 ti,otap-del-sel-legacy = <0x0>;
762 ti,otap-del-sel-sd-hs = <0x0>;
763 ti,otap-del-sel-sdr12 = <0xf>;
764 ti,otap-del-sel-sdr25 = <0xf>;
765 ti,otap-del-sel-sdr50 = <0xc>;
766 ti,otap-del-sel-sdr104 = <0x5>;
767 ti,otap-del-sel-ddr50 = <0xc>;
768 ti,itap-del-sel-legacy = <0x0>;
769 ti,itap-del-sel-sd-hs = <0x0>;
770 ti,itap-del-sel-sdr12 = <0x0>;
771 ti,itap-del-sel-sdr25 = <0x0>;
772 ti,itap-del-sel-ddr50 = <0x2>;
773 ti,clkbuf-sel = <0x7>;
774 ti,trm-icp = <0x8>;
775 dma-coherent;
780 compatible = "simple-bus";
781 #address-cells = <2>;
782 #size-cells = <2>;
784 ti,sci-dev-id = <224>;
785 dma-coherent;
786 dma-ranges;
788 main_navss_intr: interrupt-controller@310e0000 {
789 compatible = "ti,sci-intr";
791 ti,intr-trigger-type = <4>;
792 interrupt-controller;
793 interrupt-parent = <&gic500>;
794 #interrupt-cells = <1>;
796 ti,sci-dev-id = <227>;
797 ti,interrupt-ranges = <0 64 64>,
802 main_udmass_inta: msi-controller@33d00000 {
803 compatible = "ti,sci-inta";
805 interrupt-controller;
806 #interrupt-cells = <0>;
807 interrupt-parent = <&main_navss_intr>;
808 msi-controller;
810 ti,sci-dev-id = <265>;
811 ti,interrupt-ranges = <0 0 256>;
812 ti,unmapped-event-sources = <&main_bcdma_csi>;
816 compatible = "ti,am654-secure-proxy";
817 #mbox-cells = <1>;
818 reg-names = "target_data", "rt", "scfg";
822 interrupt-names = "rx_011";
824 bootph-all;
828 compatible = "ti,am654-hwspinlock";
830 #hwlock-cells = <1>;
834 compatible = "ti,am654-mailbox";
836 #mbox-cells = <1>;
837 ti,mbox-num-users = <4>;
838 ti,mbox-num-fifos = <16>;
839 interrupt-parent = <&main_navss_intr>;
844 compatible = "ti,am654-mailbox";
846 #mbox-cells = <1>;
847 ti,mbox-num-users = <4>;
848 ti,mbox-num-fifos = <16>;
849 interrupt-parent = <&main_navss_intr>;
854 compatible = "ti,am654-mailbox";
856 #mbox-cells = <1>;
857 ti,mbox-num-users = <4>;
858 ti,mbox-num-fifos = <16>;
859 interrupt-parent = <&main_navss_intr>;
864 compatible = "ti,am654-mailbox";
866 #mbox-cells = <1>;
867 ti,mbox-num-users = <4>;
868 ti,mbox-num-fifos = <16>;
869 interrupt-parent = <&main_navss_intr>;
874 compatible = "ti,am654-mailbox";
876 #mbox-cells = <1>;
877 ti,mbox-num-users = <4>;
878 ti,mbox-num-fifos = <16>;
879 interrupt-parent = <&main_navss_intr>;
884 compatible = "ti,am654-mailbox";
886 #mbox-cells = <1>;
887 ti,mbox-num-users = <4>;
888 ti,mbox-num-fifos = <16>;
889 interrupt-parent = <&main_navss_intr>;
894 compatible = "ti,am654-mailbox";
896 #mbox-cells = <1>;
897 ti,mbox-num-users = <4>;
898 ti,mbox-num-fifos = <16>;
899 interrupt-parent = <&main_navss_intr>;
904 compatible = "ti,am654-mailbox";
906 #mbox-cells = <1>;
907 ti,mbox-num-users = <4>;
908 ti,mbox-num-fifos = <16>;
909 interrupt-parent = <&main_navss_intr>;
914 compatible = "ti,am654-mailbox";
916 #mbox-cells = <1>;
917 ti,mbox-num-users = <4>;
918 ti,mbox-num-fifos = <16>;
919 interrupt-parent = <&main_navss_intr>;
924 compatible = "ti,am654-mailbox";
926 #mbox-cells = <1>;
927 ti,mbox-num-users = <4>;
928 ti,mbox-num-fifos = <16>;
929 interrupt-parent = <&main_navss_intr>;
934 compatible = "ti,am654-mailbox";
936 #mbox-cells = <1>;
937 ti,mbox-num-users = <4>;
938 ti,mbox-num-fifos = <16>;
939 interrupt-parent = <&main_navss_intr>;
944 compatible = "ti,am654-mailbox";
946 #mbox-cells = <1>;
947 ti,mbox-num-users = <4>;
948 ti,mbox-num-fifos = <16>;
949 interrupt-parent = <&main_navss_intr>;
954 compatible = "ti,am654-mailbox";
956 #mbox-cells = <1>;
957 ti,mbox-num-users = <4>;
958 ti,mbox-num-fifos = <16>;
959 interrupt-parent = <&main_navss_intr>;
964 compatible = "ti,am654-mailbox";
966 #mbox-cells = <1>;
967 ti,mbox-num-users = <4>;
968 ti,mbox-num-fifos = <16>;
969 interrupt-parent = <&main_navss_intr>;
974 compatible = "ti,am654-mailbox";
976 #mbox-cells = <1>;
977 ti,mbox-num-users = <4>;
978 ti,mbox-num-fifos = <16>;
979 interrupt-parent = <&main_navss_intr>;
984 compatible = "ti,am654-mailbox";
986 #mbox-cells = <1>;
987 ti,mbox-num-users = <4>;
988 ti,mbox-num-fifos = <16>;
989 interrupt-parent = <&main_navss_intr>;
994 compatible = "ti,am654-mailbox";
996 #mbox-cells = <1>;
997 ti,mbox-num-users = <4>;
998 ti,mbox-num-fifos = <16>;
999 interrupt-parent = <&main_navss_intr>;
1004 compatible = "ti,am654-mailbox";
1006 #mbox-cells = <1>;
1007 ti,mbox-num-users = <4>;
1008 ti,mbox-num-fifos = <16>;
1009 interrupt-parent = <&main_navss_intr>;
1014 compatible = "ti,am654-mailbox";
1016 #mbox-cells = <1>;
1017 ti,mbox-num-users = <4>;
1018 ti,mbox-num-fifos = <16>;
1019 interrupt-parent = <&main_navss_intr>;
1024 compatible = "ti,am654-mailbox";
1026 #mbox-cells = <1>;
1027 ti,mbox-num-users = <4>;
1028 ti,mbox-num-fifos = <16>;
1029 interrupt-parent = <&main_navss_intr>;
1034 compatible = "ti,am654-mailbox";
1036 #mbox-cells = <1>;
1037 ti,mbox-num-users = <4>;
1038 ti,mbox-num-fifos = <16>;
1039 interrupt-parent = <&main_navss_intr>;
1044 compatible = "ti,am654-mailbox";
1046 #mbox-cells = <1>;
1047 ti,mbox-num-users = <4>;
1048 ti,mbox-num-fifos = <16>;
1049 interrupt-parent = <&main_navss_intr>;
1054 compatible = "ti,am654-mailbox";
1056 #mbox-cells = <1>;
1057 ti,mbox-num-users = <4>;
1058 ti,mbox-num-fifos = <16>;
1059 interrupt-parent = <&main_navss_intr>;
1064 compatible = "ti,am654-mailbox";
1066 #mbox-cells = <1>;
1067 ti,mbox-num-users = <4>;
1068 ti,mbox-num-fifos = <16>;
1069 interrupt-parent = <&main_navss_intr>;
1074 compatible = "ti,am654-navss-ringacc";
1080 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
1081 ti,num-rings = <1024>;
1082 ti,sci-rm-range-gp-rings = <0x1>;
1084 ti,sci-dev-id = <259>;
1085 msi-parent = <&main_udmass_inta>;
1088 main_udmap: dma-controller@31150000 {
1089 compatible = "ti,j721e-navss-main-udmap";
1096 reg-names = "gcfg", "rchanrt", "tchanrt",
1098 msi-parent = <&main_udmass_inta>;
1099 #dma-cells = <1>;
1102 ti,sci-dev-id = <263>;
1105 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
1108 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
1111 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
1114 main_bcdma_csi: dma-controller@311a0000 {
1115 compatible = "ti,j721s2-dmss-bcdma-csi";
1120 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
1121 msi-parent = <&main_udmass_inta>;
1122 #dma-cells = <3>;
1124 ti,sci-dev-id = <225>;
1125 ti,sci-rm-range-rchan = <0x21>;
1126 ti,sci-rm-range-tchan = <0x22>;
1130 compatible = "ti,j721e-cpts";
1132 reg-names = "cpts";
1134 clock-names = "cpts";
1135 assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */
1136 assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */
1137 interrupts-extended = <&main_navss_intr 391>;
1138 interrupt-names = "cpts";
1139 ti,cpts-periodic-outputs = <6>;
1140 ti,cpts-ext-ts-inputs = <8>;
1145 compatible = "ti,j721e-cpsw-nuss";
1147 reg-names = "cpsw_nuss";
1149 #address-cells = <2>;
1150 #size-cells = <2>;
1151 dma-coherent;
1153 clock-names = "fck";
1154 power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
1165 dma-names = "tx0", "tx1", "tx2", "tx3",
1171 ethernet-ports {
1172 #address-cells = <1>;
1173 #size-cells = <0>;
1177 ti,mac-only;
1185 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1187 #address-cells = <1>;
1188 #size-cells = <0>;
1190 clock-names = "fck";
1196 compatible = "ti,am65-cpts";
1199 clock-names = "cpts";
1200 interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1201 interrupt-names = "cpts";
1202 ti,cpts-ext-ts-inputs = <4>;
1203 ti,cpts-periodic-outputs = <2>;
1207 usbss0: cdns-usb@4104000 {
1208 compatible = "ti,j721e-usb";
1211 clock-names = "ref", "lpm";
1212 assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
1213 assigned-clock-parents = <&k3_clks 360 17>;
1214 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
1215 #address-cells = <2>;
1216 #size-cells = <2>;
1218 dma-coherent;
1227 reg-names = "otg", "xhci", "dev";
1231 interrupt-names = "host", "peripheral", "otg";
1232 maximum-speed = "super-speed";
1238 compatible = "ti,j721e-csi2rx-shim";
1241 #address-cells = <2>;
1242 #size-cells = <2>;
1244 dma-names = "rx0";
1245 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
1248 cdns_csi2rx0: csi-bridge@4504000 {
1249 compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
1253 clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
1256 phy-names = "dphy";
1259 #address-cells = <1>;
1260 #size-cells = <0>;
1291 compatible = "ti,j721e-csi2rx-shim";
1294 #address-cells = <2>;
1295 #size-cells = <2>;
1297 dma-names = "rx0";
1298 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
1301 cdns_csi2rx1: csi-bridge@4514000 {
1302 compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
1306 clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
1309 phy-names = "dphy";
1312 #address-cells = <1>;
1313 #size-cells = <0>;
1344 compatible = "cdns,dphy-rx";
1346 #phy-cells = <0>;
1347 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1352 compatible = "cdns,dphy-rx";
1354 #phy-cells = <0>;
1355 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
1360 compatible = "ti,j721s2-wiz-10g";
1361 #address-cells = <1>;
1362 #size-cells = <1>;
1363 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
1365 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
1366 num-lanes = <4>;
1367 #reset-cells = <1>;
1368 #clock-cells = <1>;
1371 assigned-clocks = <&k3_clks 365 3>;
1372 assigned-clock-parents = <&k3_clks 365 7>;
1375 compatible = "ti,j721e-serdes-10g";
1377 reg-names = "torrent_phy";
1379 reset-names = "torrent_reset";
1382 clock-names = "refclk", "phy_en_refclk";
1383 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
1386 assigned-clock-parents = <&k3_clks 365 3>,
1389 #address-cells = <1>;
1390 #size-cells = <0>;
1391 #clock-cells = <1>;
1398 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
1403 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
1404 interrupt-names = "link_state";
1407 ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
1408 max-link-speed = <3>;
1409 num-lanes = <4>;
1410 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
1412 clock-names = "fck";
1413 #address-cells = <3>;
1414 #size-cells = <2>;
1415 bus-range = <0x0 0xff>;
1416 vendor-id = <0x104c>;
1417 device-id = <0xb013>;
1418 msi-map = <0x0 &gic_its 0x0 0x10000>;
1419 dma-coherent;
1421 … 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4…
1422 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1423 #interrupt-cells = <1>;
1424 interrupt-map-mask = <0 0 0 7>;
1425 interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
1432 pcie1_intc: interrupt-controller {
1433 interrupt-controller;
1434 #interrupt-cells = <1>;
1435 interrupt-parent = <&gic500>;
1444 reg-names = "m_can", "message_ram";
1445 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1447 clock-names = "hclk", "cclk";
1450 interrupt-names = "int0", "int1";
1451 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1459 reg-names = "m_can", "message_ram";
1460 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
1462 clock-names = "hclk", "cclk";
1465 interrupt-names = "int0", "int1";
1466 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1474 reg-names = "m_can", "message_ram";
1475 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
1477 clock-names = "hclk", "cclk";
1480 interrupt-names = "int0", "int1";
1481 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1489 reg-names = "m_can", "message_ram";
1490 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1492 clock-names = "hclk", "cclk";
1495 interrupt-names = "int0", "int1";
1496 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1504 reg-names = "m_can", "message_ram";
1505 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
1507 clock-names = "hclk", "cclk";
1510 interrupt-names = "int0", "int1";
1511 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1519 reg-names = "m_can", "message_ram";
1520 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
1522 clock-names = "hclk", "cclk";
1525 interrupt-names = "int0", "int1";
1526 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1534 reg-names = "m_can", "message_ram";
1535 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1537 clock-names = "hclk", "cclk";
1540 interrupt-names = "int0", "int1";
1541 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1549 reg-names = "m_can", "message_ram";
1550 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1552 clock-names = "hclk", "cclk";
1555 interrupt-names = "int0", "int1";
1556 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1564 reg-names = "m_can", "message_ram";
1565 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1567 clock-names = "hclk", "cclk";
1570 interrupt-names = "int0", "int1";
1571 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1579 reg-names = "m_can", "message_ram";
1580 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1582 clock-names = "hclk", "cclk";
1585 interrupt-names = "int0", "int1";
1586 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1594 reg-names = "m_can", "message_ram";
1595 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1597 clock-names = "hclk", "cclk";
1600 interrupt-names = "int0", "int1";
1601 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1609 reg-names = "m_can", "message_ram";
1610 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1612 clock-names = "hclk", "cclk";
1615 interrupt-names = "int0", "int1";
1616 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1624 reg-names = "m_can", "message_ram";
1625 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
1627 clock-names = "hclk", "cclk";
1630 interrupt-names = "int0", "int1";
1631 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1639 reg-names = "m_can", "message_ram";
1640 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
1642 clock-names = "hclk", "cclk";
1645 interrupt-names = "int0", "int1";
1646 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1654 reg-names = "m_can", "message_ram";
1655 power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
1657 clock-names = "hclk", "cclk";
1660 interrupt-names = "int0", "int1";
1661 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1669 reg-names = "m_can", "message_ram";
1670 power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>;
1672 clock-names = "hclk", "cclk";
1675 interrupt-names = "int0", "int1";
1676 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1684 reg-names = "m_can", "message_ram";
1685 power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
1687 clock-names = "hclk", "cclk";
1690 interrupt-names = "int0", "int1";
1691 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1699 reg-names = "m_can", "message_ram";
1700 power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>;
1702 clock-names = "hclk", "cclk";
1705 interrupt-names = "int0", "int1";
1706 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1711 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1714 #address-cells = <1>;
1715 #size-cells = <0>;
1716 power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>;
1722 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1725 #address-cells = <1>;
1726 #size-cells = <0>;
1727 power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>;
1733 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1736 #address-cells = <1>;
1737 #size-cells = <0>;
1738 power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>;
1744 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1747 #address-cells = <1>;
1748 #size-cells = <0>;
1749 power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>;
1755 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1758 #address-cells = <1>;
1759 #size-cells = <0>;
1760 power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>;
1766 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1769 #address-cells = <1>;
1770 #size-cells = <0>;
1771 power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>;
1777 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1780 #address-cells = <1>;
1781 #size-cells = <0>;
1782 power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
1788 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1791 #address-cells = <1>;
1792 #size-cells = <0>;
1793 power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>;
1799 compatible = "ti,j721e-dss";
1817 reg-names = "common_m", "common_s0",
1828 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1829 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
1834 interrupt-names = "common_m",
1845 compatible = "ti,j721s2-r5fss";
1846 ti,cluster-mode = <1>;
1847 #address-cells = <1>;
1848 #size-cells = <1>;
1851 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1854 compatible = "ti,j721s2-r5f";
1857 reg-names = "atcm", "btcm";
1859 ti,sci-dev-id = <279>;
1860 ti,sci-proc-ids = <0x06 0xff>;
1862 firmware-name = "j721s2-main-r5f0_0-fw";
1863 ti,atcm-enable = <1>;
1864 ti,btcm-enable = <1>;
1869 compatible = "ti,j721s2-r5f";
1872 reg-names = "atcm", "btcm";
1874 ti,sci-dev-id = <280>;
1875 ti,sci-proc-ids = <0x07 0xff>;
1877 firmware-name = "j721s2-main-r5f0_1-fw";
1878 ti,atcm-enable = <1>;
1879 ti,btcm-enable = <1>;
1885 compatible = "ti,j721s2-r5fss";
1886 ti,cluster-mode = <1>;
1887 #address-cells = <1>;
1888 #size-cells = <1>;
1891 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
1894 compatible = "ti,j721s2-r5f";
1897 reg-names = "atcm", "btcm";
1899 ti,sci-dev-id = <281>;
1900 ti,sci-proc-ids = <0x08 0xff>;
1902 firmware-name = "j721s2-main-r5f1_0-fw";
1903 ti,atcm-enable = <1>;
1904 ti,btcm-enable = <1>;
1909 compatible = "ti,j721s2-r5f";
1912 reg-names = "atcm", "btcm";
1914 ti,sci-dev-id = <282>;
1915 ti,sci-proc-ids = <0x09 0xff>;
1917 firmware-name = "j721s2-main-r5f1_1-fw";
1918 ti,atcm-enable = <1>;
1919 ti,btcm-enable = <1>;
1925 compatible = "ti,j721s2-c71-dsp";
1928 reg-names = "l2sram", "l1dram";
1930 ti,sci-dev-id = <8>;
1931 ti,sci-proc-ids = <0x30 0xff>;
1933 firmware-name = "j721s2-c71_0-fw";
1938 compatible = "ti,j721s2-c71-dsp";
1941 reg-names = "l2sram", "l1dram";
1943 ti,sci-dev-id = <11>;
1944 ti,sci-proc-ids = <0x31 0xff>;
1946 firmware-name = "j721s2-c71_1-fw";
1951 compatible = "ti,j721e-esm";
1953 ti,esm-pins = <688>, <689>;
1954 bootph-pre-ram;
1958 compatible = "ti,j7-rti-wdt";
1961 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
1962 assigned-clocks = <&k3_clks 286 1>;
1963 assigned-clock-parents = <&k3_clks 286 5>;
1967 compatible = "ti,j7-rti-wdt";
1970 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
1971 assigned-clocks = <&k3_clks 287 1>;
1972 assigned-clock-parents = <&k3_clks 287 5>;
1981 compatible = "ti,j7-rti-wdt";
1984 power-domains = <&k3_pds 290 TI_SCI_PD_EXCLUSIVE>;
1985 assigned-clocks = <&k3_clks 290 1>;
1986 assigned-clock-parents = <&k3_clks 290 5>;
1992 compatible = "ti,j7-rti-wdt";
1995 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
1996 assigned-clocks = <&k3_clks 288 1>;
1997 assigned-clock-parents = <&k3_clks 288 5>;
2003 compatible = "ti,j7-rti-wdt";
2006 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
2007 assigned-clocks = <&k3_clks 289 1>;
2008 assigned-clock-parents = <&k3_clks 289 5>;
2014 compatible = "ti,j7-rti-wdt";
2017 power-domains = <&k3_pds 291 TI_SCI_PD_EXCLUSIVE>;
2018 assigned-clocks = <&k3_clks 291 1>;
2019 assigned-clock-parents = <&k3_clks 291 5>;
2025 compatible = "ti,j7-rti-wdt";
2028 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
2029 assigned-clocks = <&k3_clks 292 1>;
2030 assigned-clock-parents = <&k3_clks 292 5>;
2036 compatible = "ti,j7-rti-wdt";
2039 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
2040 assigned-clocks = <&k3_clks 293 1>;
2041 assigned-clock-parents = <&k3_clks 293 5>;
2047 compatible = "ti,j7-rti-wdt";
2050 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
2051 assigned-clocks = <&k3_clks 294 1>;
2052 assigned-clock-parents = <&k3_clks 294 5>;
2058 compatible = "ti,j721s2-gpu", "img,img-bxs-4-64", "img,img-rogue";
2061 clock-names = "core";
2062 assigned-clocks = <&k3_clks 130 1>;
2063 assigned-clock-rates = <800000000>;
2065 power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>,
2067 power-domain-names = "a", "b";
2068 dma-coherent;
2072 compatible = "ti,am33xx-mcasp-audio";
2075 reg-names = "mpu","dat";
2078 interrupt-names = "tx", "rx";
2080 dma-names = "tx", "rx";
2082 clock-names = "fck";
2083 assigned-clocks = <&k3_clks 209 0>;
2084 assigned-clock-parents = <&k3_clks 209 1>;
2085 power-domains = <&k3_pds 209 TI_SCI_PD_EXCLUSIVE>;
2090 compatible = "ti,am33xx-mcasp-audio";
2093 reg-names = "mpu","dat";
2096 interrupt-names = "tx", "rx";
2098 dma-names = "tx", "rx";
2100 clock-names = "fck";
2101 assigned-clocks = <&k3_clks 210 0>;
2102 assigned-clock-parents = <&k3_clks 210 1>;
2103 power-domains = <&k3_pds 210 TI_SCI_PD_EXCLUSIVE>;
2108 compatible = "ti,am33xx-mcasp-audio";
2111 reg-names = "mpu","dat";
2114 interrupt-names = "tx", "rx";
2116 dma-names = "tx", "rx";
2118 clock-names = "fck";
2119 assigned-clocks = <&k3_clks 211 0>;
2120 assigned-clock-parents = <&k3_clks 211 1>;
2121 power-domains = <&k3_pds 211 TI_SCI_PD_EXCLUSIVE>;
2126 compatible = "ti,am33xx-mcasp-audio";
2129 reg-names = "mpu","dat";
2132 interrupt-names = "tx", "rx";
2134 dma-names = "tx", "rx";
2136 clock-names = "fck";
2137 assigned-clocks = <&k3_clks 212 0>;
2138 assigned-clock-parents = <&k3_clks 212 1>;
2139 power-domains = <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>;
2144 compatible = "ti,am33xx-mcasp-audio";
2147 reg-names = "mpu","dat";
2150 interrupt-names = "tx", "rx";
2152 dma-names = "tx", "rx";
2154 clock-names = "fck";
2155 assigned-clocks = <&k3_clks 213 0>;
2156 assigned-clock-parents = <&k3_clks 213 1>;
2157 power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>;