Lines Matching +full:0 +full:x33000000
13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x0 0x70000000 0x0 0x400000>;
25 ranges = <0x0 0x0 0x70000000 0x400000>;
27 atf-sram@0 {
28 reg = <0x0 0x20000>;
32 reg = <0x1f0000 0x10000>;
36 reg = <0x200000 0x200000>;
42 reg = <0x00 0x00104000 0x00 0x18000>;
45 ranges = <0x00 0x00 0x00104000 0x18000>;
47 usb_serdes_mux: mux-controller@0 {
49 reg = <0x0 0x4>;
51 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
56 reg = <0x34 0x4>;
62 reg = <0x74 0x4>;
67 reg = <0x80 0x10>;
69 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
70 <0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */
75 reg = <0x140 0x18>;
83 reg = <0x00 0x3000000 0x00 0x100>;
85 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>;
93 reg = <0x00 0x3010000 0x00 0x100>;
95 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>;
103 reg = <0x00 0x3020000 0x00 0x100>;
105 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>;
113 reg = <0x00 0x3030000 0x00 0x100>;
115 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>;
123 reg = <0x00 0x3040000 0x00 0x100>;
125 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>;
133 reg = <0x00 0x3050000 0x00 0x100>;
135 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>;
147 reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */
148 <0x00 0x01900000 0x00 0x100000>, /* GICR */
149 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
150 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
151 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
158 reg = <0x00 0x01820000 0x00 0x10000>;
159 socionext,synquacer-pre-its = <0x1000000 0x400000>;
167 reg = <0x00 0x00a00000 0x00 0x800>;
179 /* Proxy 0 addressing */
180 reg = <0x0 0x11c000 0x0 0x120>;
183 pinctrl-single,function-mask = <0xffffffff>;
189 reg = <0x00 0x104200 0x00 0x50>;
192 pinctrl-single,function-mask = <0x00000007>;
198 reg = <0x00 0x104280 0x00 0x20>;
201 pinctrl-single,function-mask = <0x0000001f>;
206 reg = <0x00 0x04e00000 0x00 0x1200>;
210 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
212 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
213 <&main_udmap 0x4a41>;
218 reg = <0x00 0x04e10000 0x00 0x7d>;
225 reg = <0x00 0x2400000 0x00 0x400>;
237 reg = <0x00 0x2410000 0x00 0x400>;
249 reg = <0x00 0x2420000 0x00 0x400>;
261 reg = <0x00 0x2430000 0x00 0x400>;
273 reg = <0x00 0x2440000 0x00 0x400>;
285 reg = <0x00 0x2450000 0x00 0x400>;
297 reg = <0x00 0x2460000 0x00 0x400>;
309 reg = <0x00 0x2470000 0x00 0x400>;
321 reg = <0x00 0x2480000 0x00 0x400>;
333 reg = <0x00 0x2490000 0x00 0x400>;
345 reg = <0x00 0x24a0000 0x00 0x400>;
357 reg = <0x00 0x24b0000 0x00 0x400>;
369 reg = <0x00 0x24c0000 0x00 0x400>;
381 reg = <0x00 0x24d0000 0x00 0x400>;
393 reg = <0x00 0x24e0000 0x00 0x400>;
405 reg = <0x00 0x24f0000 0x00 0x400>;
417 reg = <0x00 0x2500000 0x00 0x400>;
429 reg = <0x00 0x2510000 0x00 0x400>;
441 reg = <0x00 0x2520000 0x00 0x400>;
453 reg = <0x00 0x2530000 0x00 0x400>;
465 reg = <0x00 0x02800000 0x00 0x200>;
475 reg = <0x00 0x02810000 0x00 0x200>;
485 reg = <0x00 0x02820000 0x00 0x200>;
495 reg = <0x00 0x02830000 0x00 0x200>;
505 reg = <0x00 0x02840000 0x00 0x200>;
515 reg = <0x00 0x02850000 0x00 0x200>;
525 reg = <0x00 0x02860000 0x00 0x200>;
535 reg = <0x00 0x02870000 0x00 0x200>;
545 reg = <0x00 0x02880000 0x00 0x200>;
555 reg = <0x00 0x02890000 0x00 0x200>;
565 reg = <0x00 0x00600000 0x00 0x100>;
573 ti,davinci-gpio-unbanked = <0>;
575 clocks = <&k3_clks 111 0>;
582 reg = <0x00 0x00610000 0x00 0x100>;
590 ti,davinci-gpio-unbanked = <0>;
592 clocks = <&k3_clks 112 0>;
599 reg = <0x00 0x00620000 0x00 0x100>;
607 ti,davinci-gpio-unbanked = <0>;
609 clocks = <&k3_clks 113 0>;
616 reg = <0x00 0x00630000 0x00 0x100>;
624 ti,davinci-gpio-unbanked = <0>;
626 clocks = <&k3_clks 114 0>;
633 reg = <0x00 0x02000000 0x00 0x100>;
636 #size-cells = <0>;
644 reg = <0x00 0x02010000 0x00 0x100>;
647 #size-cells = <0>;
656 reg = <0x00 0x02020000 0x00 0x100>;
659 #size-cells = <0>;
668 reg = <0x00 0x02030000 0x00 0x100>;
671 #size-cells = <0>;
680 reg = <0x00 0x02040000 0x00 0x100>;
683 #size-cells = <0>;
692 reg = <0x00 0x02050000 0x00 0x100>;
695 #size-cells = <0>;
704 reg = <0x00 0x02060000 0x00 0x100>;
707 #size-cells = <0>;
716 reg = <0x00 0x4210000 0x00 0x10000>;
724 reg = <0x00 0x04f80000 0x00 0x1000>,
725 <0x00 0x04f88000 0x00 0x400>;
733 ti,otap-del-sel-legacy = <0x0>;
734 ti,otap-del-sel-mmc-hs = <0x0>;
735 ti,otap-del-sel-ddr52 = <0x6>;
736 ti,otap-del-sel-hs200 = <0x8>;
737 ti,otap-del-sel-hs400 = <0x5>;
738 ti,itap-del-sel-legacy = <0x10>;
739 ti,itap-del-sel-mmc-hs = <0xa>;
740 ti,strobe-sel = <0x77>;
741 ti,clkbuf-sel = <0x7>;
742 ti,trm-icp = <0x8>;
752 reg = <0x00 0x04fb0000 0x00 0x1000>,
753 <0x00 0x04fb8000 0x00 0x400>;
761 ti,otap-del-sel-legacy = <0x0>;
762 ti,otap-del-sel-sd-hs = <0x0>;
763 ti,otap-del-sel-sdr12 = <0xf>;
764 ti,otap-del-sel-sdr25 = <0xf>;
765 ti,otap-del-sel-sdr50 = <0xc>;
766 ti,otap-del-sel-sdr104 = <0x5>;
767 ti,otap-del-sel-ddr50 = <0xc>;
768 ti,itap-del-sel-legacy = <0x0>;
769 ti,itap-del-sel-sd-hs = <0x0>;
770 ti,itap-del-sel-sdr12 = <0x0>;
771 ti,itap-del-sel-sdr25 = <0x0>;
772 ti,itap-del-sel-ddr50 = <0x2>;
773 ti,clkbuf-sel = <0x7>;
774 ti,trm-icp = <0x8>;
783 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
790 reg = <0x00 0x310e0000 0x00 0x4000>;
797 ti,interrupt-ranges = <0 64 64>,
804 reg = <0x00 0x33d00000 0x00 0x100000>;
806 #interrupt-cells = <0>;
811 ti,interrupt-ranges = <0 0 256>;
819 reg = <0x00 0x32c00000 0x00 0x100000>,
820 <0x00 0x32400000 0x00 0x100000>,
821 <0x00 0x32800000 0x00 0x100000>;
829 reg = <0x00 0x30e00000 0x00 0x1000>;
835 reg = <0x00 0x31f80000 0x00 0x200>;
845 reg = <0x00 0x31f81000 0x00 0x200>;
855 reg = <0x00 0x31f82000 0x00 0x200>;
865 reg = <0x00 0x31f83000 0x00 0x200>;
875 reg = <0x00 0x31f84000 0x00 0x200>;
885 reg = <0x00 0x31f85000 0x00 0x200>;
895 reg = <0x00 0x31f86000 0x00 0x200>;
905 reg = <0x00 0x31f87000 0x00 0x200>;
915 reg = <0x00 0x31f88000 0x00 0x200>;
925 reg = <0x00 0x31f89000 0x00 0x200>;
935 reg = <0x00 0x31f8a000 0x00 0x200>;
945 reg = <0x00 0x31f8b000 0x00 0x200>;
955 reg = <0x00 0x31f90000 0x00 0x200>;
965 reg = <0x00 0x31f91000 0x00 0x200>;
975 reg = <0x00 0x31f92000 0x00 0x200>;
985 reg = <0x00 0x31f93000 0x00 0x200>;
995 reg = <0x00 0x31f94000 0x00 0x200>;
1005 reg = <0x00 0x31f95000 0x00 0x200>;
1015 reg = <0x00 0x31f96000 0x00 0x200>;
1025 reg = <0x00 0x31f97000 0x00 0x200>;
1035 reg = <0x00 0x31f98000 0x00 0x200>;
1045 reg = <0x00 0x31f99000 0x00 0x200>;
1055 reg = <0x00 0x31f9a000 0x00 0x200>;
1065 reg = <0x00 0x31f9b000 0x00 0x200>;
1075 reg = <0x0 0x3c000000 0x0 0x400000>,
1076 <0x0 0x38000000 0x0 0x400000>,
1077 <0x0 0x31120000 0x0 0x100>,
1078 <0x0 0x33000000 0x0 0x40000>,
1079 <0x0 0x31080000 0x0 0x40000>;
1082 ti,sci-rm-range-gp-rings = <0x1>;
1090 reg = <0x0 0x31150000 0x0 0x100>,
1091 <0x0 0x34000000 0x0 0x80000>,
1092 <0x0 0x35000000 0x0 0x200000>,
1093 <0x0 0x30b00000 0x0 0x20000>,
1094 <0x0 0x30c00000 0x0 0x8000>,
1095 <0x0 0x30d00000 0x0 0x4000>;
1105 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
1106 <0x0f>, /* TX_HCHAN */
1107 <0x10>; /* TX_UHCHAN */
1108 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
1109 <0x0b>, /* RX_HCHAN */
1110 <0x0c>; /* RX_UHCHAN */
1111 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
1116 reg = <0x00 0x311a0000 0x00 0x100>,
1117 <0x00 0x35d00000 0x00 0x20000>,
1118 <0x00 0x35c00000 0x00 0x10000>,
1119 <0x00 0x35e00000 0x00 0x80000>;
1125 ti,sci-rm-range-rchan = <0x21>;
1126 ti,sci-rm-range-tchan = <0x22>;
1131 reg = <0x0 0x310d0000 0x0 0x400>;
1146 reg = <0x00 0xc200000 0x00 0x200000>;
1148 ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>;
1156 dmas = <&main_udmap 0xc640>,
1157 <&main_udmap 0xc641>,
1158 <&main_udmap 0xc642>,
1159 <&main_udmap 0xc643>,
1160 <&main_udmap 0xc644>,
1161 <&main_udmap 0xc645>,
1162 <&main_udmap 0xc646>,
1163 <&main_udmap 0xc647>,
1164 <&main_udmap 0x4640>;
1173 #size-cells = <0>;
1186 reg = <0x00 0xf00 0x00 0x100>;
1188 #size-cells = <0>;
1197 reg = <0x00 0x3d000 0x00 0x400>;
1209 reg = <0x00 0x04104000 0x00 0x100>;
1224 reg = <0x00 0x06000000 0x00 0x10000>,
1225 <0x00 0x06010000 0x00 0x10000>,
1226 <0x00 0x06020000 0x00 0x10000>;
1239 reg = <0x00 0x04500000 0x00 0x1000>;
1243 dmas = <&main_bcdma_csi 0 0x4940 0>;
1250 reg = <0x00 0x04504000 0x00 0x1000>;
1260 #size-cells = <0>;
1262 csi0_port0: port@0 {
1263 reg = <0>;
1292 reg = <0x00 0x04510000 0x00 0x1000>;
1296 dmas = <&main_bcdma_csi 0 0x4960 0>;
1303 reg = <0x00 0x04514000 0x00 0x1000>;
1313 #size-cells = <0>;
1315 csi1_port0: port@0 {
1316 reg = <0>;
1345 reg = <0x00 0x04580000 0x00 0x1100>;
1346 #phy-cells = <0>;
1353 reg = <0x00 0x04590000 0x00 0x1100>;
1354 #phy-cells = <0>;
1364 clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
1369 ranges = <0x5060000 0x0 0x5060000 0x10000>;
1376 reg = <0x05060000 0x00010000>;
1378 resets = <&serdes_wiz0 0>;
1390 #size-cells = <0>;
1399 reg = <0x00 0x02910000 0x00 0x1000>,
1400 <0x00 0x02917000 0x00 0x400>,
1401 <0x00 0x0d800000 0x00 0x800000>,
1402 <0x41 0x00000000 0x00 0x1000>; /* ECAM (4 KB) */
1407 ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
1415 bus-range = <0x0 0xff>;
1416 vendor-id = <0x104c>;
1417 device-id = <0xb013>;
1418 msi-map = <0x0 &gic_its 0x0 0x10000>;
1420 ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
1421 <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */
1422 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1424 interrupt-map-mask = <0 0 0 7>;
1425 interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
1426 <0 0 0 2 &pcie1_intc 0>, /* INT B */
1427 <0 0 0 3 &pcie1_intc 0>, /* INT C */
1428 <0 0 0 4 &pcie1_intc 0>; /* INT D */
1442 reg = <0x00 0x02701000 0x00 0x200>,
1443 <0x00 0x02708000 0x00 0x8000>;
1446 clocks = <&k3_clks 182 0>, <&k3_clks 182 1>;
1451 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1457 reg = <0x00 0x02711000 0x00 0x200>,
1458 <0x00 0x02718000 0x00 0x8000>;
1461 clocks = <&k3_clks 183 0>, <&k3_clks 183 1>;
1466 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1472 reg = <0x00 0x02721000 0x00 0x200>,
1473 <0x00 0x02728000 0x00 0x8000>;
1476 clocks = <&k3_clks 184 0>, <&k3_clks 184 1>;
1481 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1487 reg = <0x00 0x02731000 0x00 0x200>,
1488 <0x00 0x02738000 0x00 0x8000>;
1491 clocks = <&k3_clks 185 0>, <&k3_clks 185 1>;
1496 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1502 reg = <0x00 0x02741000 0x00 0x200>,
1503 <0x00 0x02748000 0x00 0x8000>;
1506 clocks = <&k3_clks 186 0>, <&k3_clks 186 1>;
1511 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1517 reg = <0x00 0x02751000 0x00 0x200>,
1518 <0x00 0x02758000 0x00 0x8000>;
1521 clocks = <&k3_clks 187 0>, <&k3_clks 187 1>;
1526 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1532 reg = <0x00 0x02761000 0x00 0x200>,
1533 <0x00 0x02768000 0x00 0x8000>;
1536 clocks = <&k3_clks 188 0>, <&k3_clks 188 1>;
1541 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1547 reg = <0x00 0x02771000 0x00 0x200>,
1548 <0x00 0x02778000 0x00 0x8000>;
1551 clocks = <&k3_clks 189 0>, <&k3_clks 189 1>;
1556 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1562 reg = <0x00 0x02781000 0x00 0x200>,
1563 <0x00 0x02788000 0x00 0x8000>;
1566 clocks = <&k3_clks 190 0>, <&k3_clks 190 1>;
1571 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1577 reg = <0x00 0x02791000 0x00 0x200>,
1578 <0x00 0x02798000 0x00 0x8000>;
1581 clocks = <&k3_clks 191 0>, <&k3_clks 191 1>;
1586 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1592 reg = <0x00 0x027a1000 0x00 0x200>,
1593 <0x00 0x027a8000 0x00 0x8000>;
1596 clocks = <&k3_clks 192 0>, <&k3_clks 192 1>;
1601 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1607 reg = <0x00 0x027b1000 0x00 0x200>,
1608 <0x00 0x027b8000 0x00 0x8000>;
1611 clocks = <&k3_clks 193 0>, <&k3_clks 193 1>;
1616 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1622 reg = <0x00 0x027c1000 0x00 0x200>,
1623 <0x00 0x027c8000 0x00 0x8000>;
1626 clocks = <&k3_clks 194 0>, <&k3_clks 194 1>;
1631 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1637 reg = <0x00 0x027d1000 0x00 0x200>,
1638 <0x00 0x027d8000 0x00 0x8000>;
1641 clocks = <&k3_clks 195 0>, <&k3_clks 195 1>;
1646 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1652 reg = <0x00 0x02681000 0x00 0x200>,
1653 <0x00 0x02688000 0x00 0x8000>;
1656 clocks = <&k3_clks 197 0>, <&k3_clks 197 1>;
1661 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1667 reg = <0x00 0x02691000 0x00 0x200>,
1668 <0x00 0x02698000 0x00 0x8000>;
1671 clocks = <&k3_clks 199 0>, <&k3_clks 199 1>;
1676 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1682 reg = <0x00 0x026a1000 0x00 0x200>,
1683 <0x00 0x026a8000 0x00 0x8000>;
1686 clocks = <&k3_clks 201 0>, <&k3_clks 201 1>;
1691 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1697 reg = <0x00 0x026b1000 0x00 0x200>,
1698 <0x00 0x026b8000 0x00 0x8000>;
1701 clocks = <&k3_clks 206 0>, <&k3_clks 206 1>;
1706 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1712 reg = <0x00 0x02100000 0x00 0x400>;
1715 #size-cells = <0>;
1723 reg = <0x00 0x02110000 0x00 0x400>;
1726 #size-cells = <0>;
1734 reg = <0x00 0x02120000 0x00 0x400>;
1737 #size-cells = <0>;
1745 reg = <0x00 0x02130000 0x00 0x400>;
1748 #size-cells = <0>;
1756 reg = <0x00 0x02140000 0x00 0x400>;
1759 #size-cells = <0>;
1767 reg = <0x00 0x02150000 0x00 0x400>;
1770 #size-cells = <0>;
1778 reg = <0x00 0x02160000 0x00 0x400>;
1781 #size-cells = <0>;
1789 reg = <0x00 0x02170000 0x00 0x400>;
1792 #size-cells = <0>;
1800 reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1801 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1802 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1803 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1804 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1805 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1806 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1807 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1808 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1809 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1810 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1811 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1812 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1813 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1814 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1815 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1816 <0x00 0x04af0000 0x00 0x10000>; /* wb */
1823 clocks = <&k3_clks 158 0>,
1849 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
1850 <0x5d00000 0x00 0x5d00000 0x20000>;
1855 reg = <0x5c00000 0x00010000>,
1856 <0x5c10000 0x00010000>;
1860 ti,sci-proc-ids = <0x06 0xff>;
1870 reg = <0x5d00000 0x00010000>,
1871 <0x5d10000 0x00010000>;
1875 ti,sci-proc-ids = <0x07 0xff>;
1889 ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
1890 <0x5f00000 0x00 0x5f00000 0x20000>;
1895 reg = <0x5e00000 0x00010000>,
1896 <0x5e10000 0x00010000>;
1900 ti,sci-proc-ids = <0x08 0xff>;
1910 reg = <0x5f00000 0x00010000>,
1911 <0x5f10000 0x00010000>;
1915 ti,sci-proc-ids = <0x09 0xff>;
1926 reg = <0x00 0x64800000 0x00 0x00080000>,
1927 <0x00 0x64e00000 0x00 0x0000c000>;
1931 ti,sci-proc-ids = <0x30 0xff>;
1939 reg = <0x00 0x65800000 0x00 0x00080000>,
1940 <0x00 0x65e00000 0x00 0x0000c000>;
1944 ti,sci-proc-ids = <0x31 0xff>;
1952 reg = <0x00 0x700000 0x00 0x1000>;
1959 reg = <0x00 0x2200000 0x00 0x100>;
1968 reg = <0x00 0x2210000 0x00 0x100>;
1982 reg = <0x00 0x22f0000 0x00 0x100>;
1993 reg = <0x00 0x2300000 0x00 0x100>;
2004 reg = <0x00 0x2310000 0x00 0x100>;
2015 reg = <0x00 0x23c0000 0x00 0x100>;
2026 reg = <0x00 0x23d0000 0x00 0x100>;
2037 reg = <0x00 0x23e0000 0x00 0x100>;
2048 reg = <0x00 0x23f0000 0x00 0x100>;
2059 reg = <0x4e 0x20000000 0x00 0x80000>;
2073 reg = <0x00 0x02b00000 0x00 0x2000>,
2074 <0x00 0x02b08000 0x00 0x1000>;
2079 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
2081 clocks = <&k3_clks 209 0>;
2083 assigned-clocks = <&k3_clks 209 0>;
2091 reg = <0x00 0x02b10000 0x00 0x2000>,
2092 <0x00 0x02b18000 0x00 0x1000>;
2097 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
2099 clocks = <&k3_clks 210 0>;
2101 assigned-clocks = <&k3_clks 210 0>;
2109 reg = <0x00 0x02b20000 0x00 0x2000>,
2110 <0x00 0x02b28000 0x00 0x1000>;
2115 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
2117 clocks = <&k3_clks 211 0>;
2119 assigned-clocks = <&k3_clks 211 0>;
2127 reg = <0x00 0x02b30000 0x00 0x2000>,
2128 <0x00 0x02b38000 0x00 0x1000>;
2133 dmas = <&main_udmap 0xc403>, <&main_udmap 0x4403>;
2135 clocks = <&k3_clks 212 0>;
2137 assigned-clocks = <&k3_clks 212 0>;
2145 reg = <0x00 0x02b40000 0x00 0x2000>,
2146 <0x00 0x02b48000 0x00 0x1000>;
2151 dmas = <&main_udmap 0xc404>, <&main_udmap 0x4404>;
2153 clocks = <&k3_clks 213 0>;
2155 assigned-clocks = <&k3_clks 213 0>;