Lines Matching +full:0 +full:x2010000
15 #clock-cells = <0>;
17 clock-frequency = <0>;
21 #clock-cells = <0>;
23 clock-frequency = <0>;
30 reg = <0x0 0x70000000 0x0 0x800000>;
33 ranges = <0x0 0x0 0x70000000 0x800000>;
35 atf-sram@0 {
36 reg = <0x0 0x20000>;
42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
45 ranges = <0x0 0x0 0x00100000 0x1c000>;
49 reg = <0x4070 0x4>;
54 reg = <0x4074 0x4>;
59 reg = <0x4078 0x4>;
64 reg = <0x407c 0x4>;
69 reg = <0x4080 0x50>;
71 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
72 <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
73 <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
74 <0x30 0x3>, <0x34 0x3>, /* SERDES3 lane0/1 select */
75 <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */
76 <0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */
88 reg = <0x4044 0x20>;
94 reg = <0x4000 0x20>;
96 mux-reg-masks = <0x0 0x8000000>, /* USB0 to SERDES0/3 mux */
97 <0x10 0x8000000>; /* USB1 to SERDES1/2 mux */
102 reg = <0x4140 0x18>;
110 reg = <0x00 0x3000000 0x00 0x100>;
112 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>;
120 reg = <0x00 0x3010000 0x00 0x100>;
122 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>;
130 reg = <0x00 0x3020000 0x00 0x100>;
132 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>;
140 reg = <0x00 0x3030000 0x00 0x100>;
142 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>;
150 reg = <0x00 0x3040000 0x00 0x100>;
152 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>;
160 reg = <0x00 0x3050000 0x00 0x100>;
162 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>;
174 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
175 <0x00 0x01900000 0x00 0x100000>, /* GICR */
176 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
177 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
178 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
185 reg = <0x00 0x01820000 0x00 0x10000>;
186 socionext,synquacer-pre-its = <0x1000000 0x400000>;
194 reg = <0x00 0x00a00000 0x00 0x800>;
208 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
216 reg = <0x0 0x310e0000 0x0 0x4000>;
223 ti,interrupt-ranges = <0 64 64>,
230 reg = <0x0 0x33d00000 0x0 0x100000>;
234 #interrupt-cells = <0>;
237 ti,interrupt-ranges = <0 0 256>;
244 reg = <0x00 0x32c00000 0x00 0x100000>,
245 <0x00 0x32400000 0x00 0x100000>,
246 <0x00 0x32800000 0x00 0x100000>;
254 reg = <0x0 0x36600000 0x0 0x100000>;
264 reg = <0x00 0x30e00000 0x00 0x1000>;
270 reg = <0x00 0x31f80000 0x00 0x200>;
280 reg = <0x00 0x31f81000 0x00 0x200>;
290 reg = <0x00 0x31f82000 0x00 0x200>;
300 reg = <0x00 0x31f83000 0x00 0x200>;
310 reg = <0x00 0x31f84000 0x00 0x200>;
320 reg = <0x00 0x31f85000 0x00 0x200>;
330 reg = <0x00 0x31f86000 0x00 0x200>;
340 reg = <0x00 0x31f87000 0x00 0x200>;
350 reg = <0x00 0x31f88000 0x00 0x200>;
360 reg = <0x00 0x31f89000 0x00 0x200>;
370 reg = <0x00 0x31f8a000 0x00 0x200>;
380 reg = <0x00 0x31f8b000 0x00 0x200>;
390 reg = <0x0 0x3c000000 0x0 0x400000>,
391 <0x0 0x38000000 0x0 0x400000>,
392 <0x0 0x31120000 0x0 0x100>,
393 <0x0 0x33000000 0x0 0x40000>,
394 <0x0 0x31080000 0x0 0x40000>;
397 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
405 reg = <0x0 0x31150000 0x0 0x100>,
406 <0x0 0x34000000 0x0 0x100000>,
407 <0x0 0x35000000 0x0 0x100000>,
408 <0x0 0x30b00000 0x0 0x20000>,
409 <0x0 0x30c00000 0x0 0x10000>,
410 <0x0 0x30d00000 0x0 0x8000>;
420 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
421 <0x0f>, /* TX_HCHAN */
422 <0x10>; /* TX_UHCHAN */
423 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
424 <0x0b>, /* RX_HCHAN */
425 <0x0c>; /* RX_UHCHAN */
426 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
431 reg = <0x0 0x310d0000 0x0 0x400>;
446 reg = <0x0 0xc000000 0x0 0x200000>;
448 ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>;
453 dmas = <&main_udmap 0xca00>,
454 <&main_udmap 0xca01>,
455 <&main_udmap 0xca02>,
456 <&main_udmap 0xca03>,
457 <&main_udmap 0xca04>,
458 <&main_udmap 0xca05>,
459 <&main_udmap 0xca06>,
460 <&main_udmap 0xca07>,
461 <&main_udmap 0x4a00>;
470 #size-cells = <0>;
530 reg = <0x0 0xf00 0x0 0x100>;
532 #size-cells = <0>;
541 reg = <0x0 0x3d000 0x0 0x400>;
553 reg = <0x0 0x4e00000 0x0 0x1200>;
557 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
559 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
560 <&main_udmap 0x4001>;
565 reg = <0x0 0x4e10000 0x0 0x7d>;
572 /* Proxy 0 addressing */
573 reg = <0x0 0x11c000 0x0 0x2b4>;
576 pinctrl-single,function-mask = <0xffffffff>;
582 reg = <0x00 0x104200 0x00 0x50>;
585 pinctrl-single,function-mask = <0x00000007>;
591 reg = <0x00 0x104280 0x00 0x20>;
594 pinctrl-single,function-mask = <0x0000001f>;
599 reg = <0x0 0x4500000 0x0 0x1000>;
603 dmas = <&main_udmap 0x4940>;
610 reg = <0x0 0x4504000 0x0 0x1000>;
611 clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>,
620 #size-cells = <0>;
622 csi0_port0: port@0 {
623 reg = <0>;
652 reg = <0x0 0x4510000 0x0 0x1000>;
656 dmas = <&main_udmap 0x4960>;
663 reg = <0x0 0x4514000 0x0 0x1000>;
664 clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>,
673 #size-cells = <0>;
675 csi1_port0: port@0 {
676 reg = <0>;
705 reg = <0x0 0x4580000 0x0 0x1100>;
706 #phy-cells = <0>;
713 reg = <0x0 0x4590000 0x0 0x1100>;
714 #phy-cells = <0>;
726 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
730 ranges = <0x5000000 0x0 0x5000000 0x10000>;
734 #clock-cells = <0>;
740 clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
741 #clock-cells = <0>;
743 assigned-clock-parents = <&k3_clks 292 0>;
747 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
748 #clock-cells = <0>;
755 #clock-cells = <0>;
760 #clock-cells = <0>;
766 reg = <0x5000000 0x10000>;
768 #size-cells = <0>;
770 resets = <&serdes_wiz0 0>;
786 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
790 ranges = <0x5010000 0x0 0x5010000 0x10000>;
794 #clock-cells = <0>;
800 clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
801 #clock-cells = <0>;
803 assigned-clock-parents = <&k3_clks 293 0>;
807 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
808 #clock-cells = <0>;
815 #clock-cells = <0>;
820 #clock-cells = <0>;
826 reg = <0x5010000 0x10000>;
828 #size-cells = <0>;
830 resets = <&serdes_wiz1 0>;
846 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
850 ranges = <0x5020000 0x0 0x5020000 0x10000>;
854 #clock-cells = <0>;
860 clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
861 #clock-cells = <0>;
863 assigned-clock-parents = <&k3_clks 294 0>;
867 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
868 #clock-cells = <0>;
875 #clock-cells = <0>;
880 #clock-cells = <0>;
886 reg = <0x5020000 0x10000>;
888 #size-cells = <0>;
890 resets = <&serdes_wiz2 0>;
906 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
910 ranges = <0x5030000 0x0 0x5030000 0x10000>;
914 #clock-cells = <0>;
920 clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
921 #clock-cells = <0>;
923 assigned-clock-parents = <&k3_clks 295 0>;
927 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
928 #clock-cells = <0>;
935 #clock-cells = <0>;
940 #clock-cells = <0>;
946 reg = <0x5030000 0x10000>;
948 #size-cells = <0>;
950 resets = <&serdes_wiz3 0>;
961 reg = <0x00 0x02900000 0x00 0x1000>,
962 <0x00 0x02907000 0x00 0x400>,
963 <0x00 0x0d000000 0x00 0x00800000>,
964 <0x40 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */
969 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
977 bus-range = <0x0 0xff>;
978 vendor-id = <0x104c>;
979 device-id = <0xb00d>;
980 msi-map = <0x0 &gic_its 0x0 0x10000>;
982 ranges = <0x01000000 0x00 0x00001000 0x40 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
983 <0x02000000 0x00 0x00101000 0x40 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */
984 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
990 reg = <0x00 0x02910000 0x00 0x1000>,
991 <0x00 0x02917000 0x00 0x400>,
992 <0x00 0x0d800000 0x00 0x00800000>,
993 <0x41 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */
998 ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
1006 bus-range = <0x0 0xff>;
1007 vendor-id = <0x104c>;
1008 device-id = <0xb00d>;
1009 msi-map = <0x0 &gic_its 0x10000 0x10000>;
1011 ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
1012 <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */
1013 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1019 reg = <0x00 0x02920000 0x00 0x1000>,
1020 <0x00 0x02927000 0x00 0x400>,
1021 <0x00 0x0e000000 0x00 0x00800000>,
1022 <0x44 0x00000000 0x00 0x00001000>;
1027 ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>;
1035 bus-range = <0x0 0xff>;
1036 vendor-id = <0x104c>;
1037 device-id = <0xb00d>;
1038 msi-map = <0x0 &gic_its 0x20000 0x10000>;
1040 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
1041 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
1042 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1048 reg = <0x00 0x02930000 0x00 0x1000>,
1049 <0x00 0x02937000 0x00 0x400>,
1050 <0x00 0x0e800000 0x00 0x00800000>,
1051 <0x44 0x10000000 0x00 0x00001000>;
1056 ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>;
1064 bus-range = <0x0 0xff>;
1065 vendor-id = <0x104c>;
1066 device-id = <0xb00d>;
1067 msi-map = <0x0 &gic_its 0x30000 0x10000>;
1069 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
1070 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
1071 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1088 ranges = <0x05050000 0x00 0x05050000 0x010000>,
1089 <0x0a030a00 0x00 0x0a030a00 0x40>;
1097 reg = <0x05050000 0x010000>,
1098 <0x0a030a00 0x40>; /* DPTX PHY */
1101 resets = <&serdes_wiz4 0>;
1112 #size-cells = <0>;
1118 reg = <0x00 0x2400000 0x00 0x400>;
1130 reg = <0x00 0x2410000 0x00 0x400>;
1134 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>;
1142 reg = <0x00 0x2420000 0x00 0x400>;
1154 reg = <0x00 0x2430000 0x00 0x400>;
1158 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>;
1166 reg = <0x00 0x2440000 0x00 0x400>;
1178 reg = <0x00 0x2450000 0x00 0x400>;
1182 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>;
1190 reg = <0x00 0x2460000 0x00 0x400>;
1202 reg = <0x00 0x2470000 0x00 0x400>;
1206 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>;
1214 reg = <0x00 0x2480000 0x00 0x400>;
1226 reg = <0x00 0x2490000 0x00 0x400>;
1230 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>;
1238 reg = <0x00 0x24a0000 0x00 0x400>;
1250 reg = <0x00 0x24b0000 0x00 0x400>;
1254 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>;
1262 reg = <0x00 0x24c0000 0x00 0x400>;
1274 reg = <0x00 0x24d0000 0x00 0x400>;
1278 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>;
1286 reg = <0x00 0x24e0000 0x00 0x400>;
1298 reg = <0x00 0x24f0000 0x00 0x400>;
1302 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>;
1310 reg = <0x00 0x2500000 0x00 0x400>;
1322 reg = <0x00 0x2510000 0x00 0x400>;
1326 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>;
1334 reg = <0x00 0x2520000 0x00 0x400>;
1346 reg = <0x00 0x2530000 0x00 0x400>;
1350 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>;
1358 reg = <0x00 0x02800000 0x00 0x100>;
1362 clocks = <&k3_clks 146 0>;
1369 reg = <0x00 0x02810000 0x00 0x100>;
1373 clocks = <&k3_clks 278 0>;
1380 reg = <0x00 0x02820000 0x00 0x100>;
1384 clocks = <&k3_clks 279 0>;
1391 reg = <0x00 0x02830000 0x00 0x100>;
1395 clocks = <&k3_clks 280 0>;
1402 reg = <0x00 0x02840000 0x00 0x100>;
1406 clocks = <&k3_clks 281 0>;
1413 reg = <0x00 0x02850000 0x00 0x100>;
1417 clocks = <&k3_clks 282 0>;
1424 reg = <0x00 0x02860000 0x00 0x100>;
1428 clocks = <&k3_clks 283 0>;
1435 reg = <0x00 0x02870000 0x00 0x100>;
1439 clocks = <&k3_clks 284 0>;
1446 reg = <0x00 0x02880000 0x00 0x100>;
1450 clocks = <&k3_clks 285 0>;
1457 reg = <0x00 0x02890000 0x00 0x100>;
1461 clocks = <&k3_clks 286 0>;
1468 reg = <0x0 0x00600000 0x0 0x100>;
1477 ti,davinci-gpio-unbanked = <0>;
1479 clocks = <&k3_clks 105 0>;
1486 reg = <0x0 0x00601000 0x0 0x100>;
1494 ti,davinci-gpio-unbanked = <0>;
1496 clocks = <&k3_clks 106 0>;
1503 reg = <0x0 0x00610000 0x0 0x100>;
1512 ti,davinci-gpio-unbanked = <0>;
1514 clocks = <&k3_clks 107 0>;
1521 reg = <0x0 0x00611000 0x0 0x100>;
1529 ti,davinci-gpio-unbanked = <0>;
1531 clocks = <&k3_clks 108 0>;
1538 reg = <0x0 0x00620000 0x0 0x100>;
1547 ti,davinci-gpio-unbanked = <0>;
1549 clocks = <&k3_clks 109 0>;
1556 reg = <0x0 0x00621000 0x0 0x100>;
1564 ti,davinci-gpio-unbanked = <0>;
1566 clocks = <&k3_clks 110 0>;
1573 reg = <0x0 0x00630000 0x0 0x100>;
1582 ti,davinci-gpio-unbanked = <0>;
1584 clocks = <&k3_clks 111 0>;
1591 reg = <0x0 0x00631000 0x0 0x100>;
1599 ti,davinci-gpio-unbanked = <0>;
1601 clocks = <&k3_clks 112 0>;
1608 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
1612 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
1618 ti,otap-del-sel-legacy = <0x0>;
1619 ti,otap-del-sel-mmc-hs = <0x0>;
1620 ti,otap-del-sel-ddr52 = <0x5>;
1621 ti,otap-del-sel-hs200 = <0x6>;
1622 ti,otap-del-sel-hs400 = <0x0>;
1623 ti,itap-del-sel-legacy = <0x10>;
1624 ti,itap-del-sel-mmc-hs = <0xa>;
1625 ti,itap-del-sel-ddr52 = <0x3>;
1626 ti,trm-icp = <0x8>;
1633 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
1637 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
1638 assigned-clocks = <&k3_clks 92 0>;
1640 ti,otap-del-sel-legacy = <0x0>;
1641 ti,otap-del-sel-sd-hs = <0x0>;
1642 ti,otap-del-sel-sdr12 = <0xf>;
1643 ti,otap-del-sel-sdr25 = <0xf>;
1644 ti,otap-del-sel-sdr50 = <0xc>;
1645 ti,otap-del-sel-ddr50 = <0xc>;
1646 ti,otap-del-sel-sdr104 = <0x5>;
1647 ti,itap-del-sel-legacy = <0x0>;
1648 ti,itap-del-sel-sd-hs = <0x0>;
1649 ti,itap-del-sel-sdr12 = <0x0>;
1650 ti,itap-del-sel-sdr25 = <0x0>;
1651 ti,itap-del-sel-ddr50 = <0x2>;
1652 ti,trm-icp = <0x8>;
1653 ti,clkbuf-sel = <0x7>;
1655 sdhci-caps-mask = <0x2 0x0>;
1661 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
1665 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
1666 assigned-clocks = <&k3_clks 93 0>;
1668 ti,otap-del-sel-legacy = <0x0>;
1669 ti,otap-del-sel-sd-hs = <0x0>;
1670 ti,otap-del-sel-sdr12 = <0xf>;
1671 ti,otap-del-sel-sdr25 = <0xf>;
1672 ti,otap-del-sel-sdr50 = <0xc>;
1673 ti,otap-del-sel-ddr50 = <0xc>;
1674 ti,otap-del-sel-sdr104 = <0x5>;
1675 ti,itap-del-sel-legacy = <0x0>;
1676 ti,itap-del-sel-sd-hs = <0x0>;
1677 ti,itap-del-sel-sdr12 = <0x0>;
1678 ti,itap-del-sel-sdr25 = <0x0>;
1679 ti,itap-del-sel-ddr50 = <0x2>;
1680 ti,trm-icp = <0x8>;
1681 ti,clkbuf-sel = <0x7>;
1683 sdhci-caps-mask = <0x2 0x0>;
1689 reg = <0x00 0x4104000 0x00 0x100>;
1702 reg = <0x00 0x6000000 0x00 0x10000>,
1703 <0x00 0x6010000 0x00 0x10000>,
1704 <0x00 0x6020000 0x00 0x10000>;
1706 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1708 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1719 reg = <0x00 0x4114000 0x00 0x100>;
1732 reg = <0x00 0x6400000 0x00 0x10000>,
1733 <0x00 0x6410000 0x00 0x10000>,
1734 <0x00 0x6420000 0x00 0x10000>;
1736 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1738 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1749 reg = <0x0 0x2000000 0x0 0x100>;
1752 #size-cells = <0>;
1754 clocks = <&k3_clks 187 0>;
1761 reg = <0x0 0x2010000 0x0 0x100>;
1764 #size-cells = <0>;
1766 clocks = <&k3_clks 188 0>;
1773 reg = <0x0 0x2020000 0x0 0x100>;
1776 #size-cells = <0>;
1778 clocks = <&k3_clks 189 0>;
1785 reg = <0x0 0x2030000 0x0 0x100>;
1788 #size-cells = <0>;
1790 clocks = <&k3_clks 190 0>;
1797 reg = <0x0 0x2040000 0x0 0x100>;
1800 #size-cells = <0>;
1802 clocks = <&k3_clks 191 0>;
1809 reg = <0x0 0x2050000 0x0 0x100>;
1812 #size-cells = <0>;
1814 clocks = <&k3_clks 192 0>;
1821 reg = <0x0 0x2060000 0x0 0x100>;
1824 #size-cells = <0>;
1826 clocks = <&k3_clks 193 0>;
1833 reg = <0x0 0x4e80000 0x0 0x100>;
1844 reg = <0x0 0x4e84000 0x0 0x10000>;
1847 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
1859 reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
1860 <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */
1872 #size-cells = <0>;
1874 port@0 {
1875 reg = <0>;
1887 <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1888 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1889 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1890 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1892 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1893 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1894 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1895 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1897 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1898 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1899 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1900 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1902 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1903 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1904 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1905 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1906 <0x00 0x04af0000 0x00 0x10000>; /* wb */
1915 clocks = <&k3_clks 152 0>,
1939 reg = <0x0 0x02b00000 0x0 0x2000>,
1940 <0x0 0x02b08000 0x0 0x1000>;
1946 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
1957 reg = <0x0 0x02b10000 0x0 0x2000>,
1958 <0x0 0x02b18000 0x0 0x1000>;
1964 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
1975 reg = <0x0 0x02b20000 0x0 0x2000>,
1976 <0x0 0x02b28000 0x0 0x1000>;
1982 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
1993 reg = <0x0 0x02b30000 0x0 0x2000>,
1994 <0x0 0x02b38000 0x0 0x1000>;
2000 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
2011 reg = <0x0 0x02b40000 0x0 0x2000>,
2012 <0x0 0x02b48000 0x0 0x1000>;
2018 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
2029 reg = <0x0 0x02b50000 0x0 0x2000>,
2030 <0x0 0x02b58000 0x0 0x1000>;
2036 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
2047 reg = <0x0 0x02b60000 0x0 0x2000>,
2048 <0x0 0x02b68000 0x0 0x1000>;
2054 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
2065 reg = <0x0 0x02b70000 0x0 0x2000>,
2066 <0x0 0x02b78000 0x0 0x1000>;
2072 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
2083 reg = <0x0 0x02b80000 0x0 0x2000>,
2084 <0x0 0x02b88000 0x0 0x1000>;
2090 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
2101 reg = <0x0 0x02b90000 0x0 0x2000>,
2102 <0x0 0x02b98000 0x0 0x1000>;
2108 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
2119 reg = <0x0 0x02ba0000 0x0 0x2000>,
2120 <0x0 0x02ba8000 0x0 0x1000>;
2126 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
2137 reg = <0x0 0x02bb0000 0x0 0x2000>,
2138 <0x0 0x02bb8000 0x0 0x1000>;
2144 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
2155 reg = <0x0 0x2200000 0x0 0x100>;
2164 reg = <0x0 0x2210000 0x0 0x100>;
2176 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
2177 <0x5d00000 0x00 0x5d00000 0x20000>;
2182 reg = <0x5c00000 0x00008000>,
2183 <0x5c10000 0x00008000>;
2187 ti,sci-proc-ids = <0x06 0xff>;
2197 reg = <0x5d00000 0x00008000>,
2198 <0x5d10000 0x00008000>;
2202 ti,sci-proc-ids = <0x07 0xff>;
2216 ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
2217 <0x5f00000 0x00 0x5f00000 0x20000>;
2222 reg = <0x5e00000 0x00008000>,
2223 <0x5e10000 0x00008000>;
2227 ti,sci-proc-ids = <0x08 0xff>;
2237 reg = <0x5f00000 0x00008000>,
2238 <0x5f10000 0x00008000>;
2242 ti,sci-proc-ids = <0x09 0xff>;
2253 reg = <0x4d 0x80800000 0x00 0x00048000>,
2254 <0x4d 0x80e00000 0x00 0x00008000>,
2255 <0x4d 0x80f00000 0x00 0x00008000>;
2259 ti,sci-proc-ids = <0x03 0xff>;
2267 reg = <0x4d 0x81800000 0x00 0x00048000>,
2268 <0x4d 0x81e00000 0x00 0x00008000>,
2269 <0x4d 0x81f00000 0x00 0x00008000>;
2273 ti,sci-proc-ids = <0x04 0xff>;
2281 reg = <0x00 0x64800000 0x00 0x00080000>,
2282 <0x00 0x64e00000 0x00 0x0000c000>;
2286 ti,sci-proc-ids = <0x30 0xff>;
2294 reg = <0x00 0xb000000 0x00 0x80000>;
2298 ranges = <0x0 0x00 0x0b000000 0x100000>;
2300 icssg0_mem: memories@0 {
2301 reg = <0x0 0x2000>,
2302 <0x2000 0x2000>,
2303 <0x10000 0x10000>;
2310 reg = <0x26000 0x200>;
2313 ranges = <0x0 0x26000 0x2000>;
2317 #size-cells = <0>;
2320 reg = <0x3c>;
2321 #clock-cells = <0>;
2329 reg = <0x30>;
2330 #clock-cells = <0>;
2341 reg = <0x32000 0x100>;
2346 reg = <0x33000 0x1000>;
2351 reg = <0x20000 0x2000>;
2370 reg = <0x34000 0x3000>,
2371 <0x22000 0x100>,
2372 <0x22400 0x100>;
2379 reg = <0x4000 0x2000>,
2380 <0x23000 0x100>,
2381 <0x23400 0x100>;
2388 reg = <0xa000 0x1800>,
2389 <0x25000 0x100>,
2390 <0x25400 0x100>;
2397 reg = <0x38000 0x3000>,
2398 <0x24000 0x100>,
2399 <0x24400 0x100>;
2406 reg = <0x6000 0x2000>,
2407 <0x23800 0x100>,
2408 <0x23c00 0x100>;
2415 reg = <0xc000 0x1800>,
2416 <0x25800 0x100>,
2417 <0x25c00 0x100>;
2424 reg = <0x32400 0x100>;
2428 #size-cells = <0>;
2436 reg = <0x00 0xb100000 0x00 0x80000>;
2440 ranges = <0x0 0x00 0x0b100000 0x100000>;
2443 reg = <0x0 0x2000>,
2444 <0x2000 0x2000>,
2445 <0x10000 0x10000>;
2452 reg = <0x26000 0x200>;
2455 ranges = <0x0 0x26000 0x2000>;
2459 #size-cells = <0>;
2462 reg = <0x3c>;
2463 #clock-cells = <0>;
2471 reg = <0x30>;
2472 #clock-cells = <0>;
2483 reg = <0x32000 0x100>;
2488 reg = <0x33000 0x1000>;
2493 reg = <0x20000 0x2000>;
2512 reg = <0x34000 0x4000>,
2513 <0x22000 0x100>,
2514 <0x22400 0x100>;
2521 reg = <0x4000 0x2000>,
2522 <0x23000 0x100>,
2523 <0x23400 0x100>;
2530 reg = <0xa000 0x1800>,
2531 <0x25000 0x100>,
2532 <0x25400 0x100>;
2539 reg = <0x38000 0x4000>,
2540 <0x24000 0x100>,
2541 <0x24400 0x100>;
2548 reg = <0x6000 0x2000>,
2549 <0x23800 0x100>,
2550 <0x23c00 0x100>;
2557 reg = <0xc000 0x1800>,
2558 <0x25800 0x100>,
2559 <0x25c00 0x100>;
2566 reg = <0x32400 0x100>;
2570 #size-cells = <0>;
2578 reg = <0x00 0x02701000 0x00 0x200>,
2579 <0x00 0x02708000 0x00 0x8000>;
2582 clocks = <&k3_clks 156 0>, <&k3_clks 156 1>;
2587 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2593 reg = <0x00 0x02711000 0x00 0x200>,
2594 <0x00 0x02718000 0x00 0x8000>;
2597 clocks = <&k3_clks 158 0>, <&k3_clks 158 1>;
2602 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2608 reg = <0x00 0x02721000 0x00 0x200>,
2609 <0x00 0x02728000 0x00 0x8000>;
2612 clocks = <&k3_clks 160 0>, <&k3_clks 160 1>;
2617 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2623 reg = <0x00 0x02731000 0x00 0x200>,
2624 <0x00 0x02738000 0x00 0x8000>;
2627 clocks = <&k3_clks 161 0>, <&k3_clks 161 1>;
2632 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2638 reg = <0x00 0x02741000 0x00 0x200>,
2639 <0x00 0x02748000 0x00 0x8000>;
2642 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>;
2647 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2653 reg = <0x00 0x02751000 0x00 0x200>,
2654 <0x00 0x02758000 0x00 0x8000>;
2657 clocks = <&k3_clks 163 0>, <&k3_clks 163 1>;
2662 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2668 reg = <0x00 0x02761000 0x00 0x200>,
2669 <0x00 0x02768000 0x00 0x8000>;
2672 clocks = <&k3_clks 164 0>, <&k3_clks 164 1>;
2677 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2683 reg = <0x00 0x02771000 0x00 0x200>,
2684 <0x00 0x02778000 0x00 0x8000>;
2687 clocks = <&k3_clks 165 0>, <&k3_clks 165 1>;
2692 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2698 reg = <0x00 0x02781000 0x00 0x200>,
2699 <0x00 0x02788000 0x00 0x8000>;
2702 clocks = <&k3_clks 166 0>, <&k3_clks 166 1>;
2707 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2713 reg = <0x00 0x02791000 0x00 0x200>,
2714 <0x00 0x02798000 0x00 0x8000>;
2717 clocks = <&k3_clks 167 0>, <&k3_clks 167 1>;
2722 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2728 reg = <0x00 0x027a1000 0x00 0x200>,
2729 <0x00 0x027a8000 0x00 0x8000>;
2732 clocks = <&k3_clks 168 0>, <&k3_clks 168 1>;
2737 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2743 reg = <0x00 0x027b1000 0x00 0x200>,
2744 <0x00 0x027b8000 0x00 0x8000>;
2747 clocks = <&k3_clks 169 0>, <&k3_clks 169 1>;
2752 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2758 reg = <0x00 0x027c1000 0x00 0x200>,
2759 <0x00 0x027c8000 0x00 0x8000>;
2762 clocks = <&k3_clks 170 0>, <&k3_clks 170 1>;
2767 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2773 reg = <0x00 0x027d1000 0x00 0x200>,
2774 <0x00 0x027d8000 0x00 0x8000>;
2777 clocks = <&k3_clks 171 0>, <&k3_clks 171 1>;
2782 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2788 reg = <0x00 0x02100000 0x00 0x400>;
2791 #size-cells = <0>;
2799 reg = <0x00 0x02110000 0x00 0x400>;
2802 #size-cells = <0>;
2810 reg = <0x00 0x02120000 0x00 0x400>;
2813 #size-cells = <0>;
2821 reg = <0x00 0x02130000 0x00 0x400>;
2824 #size-cells = <0>;
2832 reg = <0x00 0x02140000 0x00 0x400>;
2835 #size-cells = <0>;
2843 reg = <0x00 0x02150000 0x00 0x400>;
2846 #size-cells = <0>;
2854 reg = <0x00 0x02160000 0x00 0x400>;
2857 #size-cells = <0>;
2865 reg = <0x00 0x02170000 0x00 0x400>;
2868 #size-cells = <0>;
2876 reg = <0x0 0x700000 0x0 0x1000>;