Lines Matching +full:0 +full:x31000000
22 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
23 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
24 <0x01 0x00000000 0x00 0x2000>, /* GICC */
25 <0x01 0x00010000 0x00 0x1000>, /* GICH */
26 <0x01 0x00020000 0x00 0x2000>; /* GICV */
35 reg = <0x00 0x01820000 0x00 0x10000>;
36 socionext,synquacer-pre-its = <0x1000000 0x400000>;
44 reg = <0x00 0x00100000 0x00 0x20000>;
47 ranges = <0x00 0x00 0x00100000 0x20000>;
51 reg = <0x4044 0x8>;
57 reg = <0x4130 0x4>;
67 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
76 reg = <0x00 0x4d000000 0x00 0x80000>,
77 <0x00 0x4a600000 0x00 0x80000>,
78 <0x00 0x4a400000 0x00 0x80000>;
86 reg = <0x00 0x48000000 0x00 0x100000>;
87 #interrupt-cells = <0>;
98 reg = <0x00 0x485c0100 0x00 0x100>,
99 <0x00 0x4c000000 0x00 0x20000>,
100 <0x00 0x4a820000 0x00 0x20000>,
101 <0x00 0x4aa40000 0x00 0x20000>,
102 <0x00 0x4bc00000 0x00 0x100000>,
103 <0x00 0x48600000 0x00 0x8000>,
104 <0x00 0x484a4000 0x00 0x2000>,
105 <0x00 0x484c2000 0x00 0x2000>,
106 <0x00 0x48420000 0x00 0x2000>;
114 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
115 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
116 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
122 reg = <0x00 0x485c0000 0x00 0x100>,
123 <0x00 0x4a800000 0x00 0x20000>,
124 <0x00 0x4aa00000 0x00 0x20000>,
125 <0x00 0x4b800000 0x00 0x200000>,
126 <0x00 0x485e0000 0x00 0x10000>,
127 <0x00 0x484a0000 0x00 0x2000>,
128 <0x00 0x484c0000 0x00 0x2000>,
129 <0x00 0x48430000 0x00 0x1000>;
138 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
139 <0x24>, /* CPSW_TX_CHAN */
140 <0x25>, /* SAUL_TX_0_CHAN */
141 <0x26>; /* SAUL_TX_1_CHAN */
142 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
143 <0x11>, /* RING_CPSW_TX_CHAN */
144 <0x12>, /* RING_SAUL_TX_0_CHAN */
145 <0x13>; /* RING_SAUL_TX_1_CHAN */
146 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
147 <0x2b>, /* CPSW_RX_CHAN */
148 <0x2d>, /* SAUL_RX_0_CHAN */
149 <0x2f>, /* SAUL_RX_1_CHAN */
150 <0x31>, /* SAUL_RX_2_CHAN */
151 <0x33>; /* SAUL_RX_3_CHAN */
152 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
153 <0x2c>, /* FLOW_CPSW_RX_CHAN */
154 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
155 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
161 ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x408000>;
169 reg = <0x00 0x4e400000 0x00 0x8000>;
170 #interrupt-cells = <0>;
177 ti,interrupt-ranges = <0 237 8>;
183 reg = <0x00 0x4e230000 0x00 0x100>,
184 <0x00 0x4e180000 0x00 0x8000>,
185 <0x00 0x4e100000 0x00 0x10000>;
192 ti,sci-rm-range-rchan = <0x21>;
203 reg = <0x00 0x44043000 0x00 0xfe0>;
227 reg = <0x00 0x40900000 0x00 0x1200>;
230 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
232 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
233 <&main_pktdma 0x7507 0>;
238 reg = <0x00 0x40910000 0x0 0x7d>;
248 reg = <0x00 0x43600000 0x00 0x10000>,
249 <0x00 0x44880000 0x00 0x20000>,
250 <0x00 0x44860000 0x00 0x20000>;
262 reg = <0x00 0xf4000 0x00 0x2b0>;
265 pinctrl-single,function-mask = <0xffffffff>;
271 reg = <0x00 0x420000 0x00 0x1000>;
279 reg = <0x00 0x2400000 0x00 0x400>;
292 reg = <0x00 0x2410000 0x00 0x400>;
304 reg = <0x00 0x2420000 0x00 0x400>;
316 reg = <0x00 0x2430000 0x00 0x400>;
328 reg = <0x00 0x2440000 0x00 0x400>;
340 reg = <0x00 0x2450000 0x00 0x400>;
352 reg = <0x00 0x2460000 0x00 0x400>;
364 reg = <0x00 0x2470000 0x00 0x400>;
376 reg = <0x00 0x02800000 0x00 0x100>;
379 clocks = <&k3_clks 146 0>;
386 reg = <0x00 0x02810000 0x00 0x100>;
389 clocks = <&k3_clks 152 0>;
396 reg = <0x00 0x02820000 0x00 0x100>;
399 clocks = <&k3_clks 153 0>;
406 reg = <0x00 0x02830000 0x00 0x100>;
409 clocks = <&k3_clks 154 0>;
416 reg = <0x00 0x02840000 0x00 0x100>;
419 clocks = <&k3_clks 155 0>;
426 reg = <0x00 0x02850000 0x00 0x100>;
429 clocks = <&k3_clks 156 0>;
436 reg = <0x00 0x02860000 0x00 0x100>;
439 clocks = <&k3_clks 158 0>;
446 reg = <0x00 0x20000000 0x00 0x100>;
449 #size-cells = <0>;
458 reg = <0x00 0x20010000 0x00 0x100>;
461 #size-cells = <0>;
470 reg = <0x00 0x20020000 0x00 0x100>;
473 #size-cells = <0>;
482 reg = <0x00 0x20030000 0x00 0x100>;
485 #size-cells = <0>;
494 reg = <0x00 0x20100000 0x00 0x400>;
497 #size-cells = <0>;
499 clocks = <&k3_clks 141 0>;
505 reg = <0x00 0x20110000 0x00 0x400>;
508 #size-cells = <0>;
510 clocks = <&k3_clks 142 0>;
516 reg = <0x00 0x20120000 0x00 0x400>;
519 #size-cells = <0>;
521 clocks = <&k3_clks 143 0>;
527 reg = <0x00 0x00a00000 0x00 0x800>;
534 ti,interrupt-ranges = <0 32 16>;
539 reg = <0x00 0x00600000 0x00 0x100>;
547 ti,davinci-gpio-unbanked = <0>;
549 clocks = <&k3_clks 77 0>;
555 reg = <0x00 0x00601000 0x00 0x100>;
563 ti,davinci-gpio-unbanked = <0>;
565 clocks = <&k3_clks 78 0>;
571 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
580 ti,clkbuf-sel = <0x7>;
581 ti,strobe-sel = <0x77>;
582 ti,trm-icp = <0x8>;
583 ti,otap-del-sel-legacy = <0x1>;
584 ti,otap-del-sel-mmc-hs = <0x1>;
585 ti,otap-del-sel-ddr52 = <0x6>;
586 ti,otap-del-sel-hs200 = <0x8>;
587 ti,otap-del-sel-hs400 = <0x5>;
588 ti,itap-del-sel-legacy = <0x10>;
589 ti,itap-del-sel-mmc-hs = <0xa>;
590 ti,itap-del-sel-ddr52 = <0x3>;
596 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
602 ti,clkbuf-sel = <0x7>;
603 ti,otap-del-sel-legacy = <0x0>;
604 ti,otap-del-sel-sd-hs = <0x0>;
605 ti,otap-del-sel-sdr12 = <0xf>;
606 ti,otap-del-sel-sdr25 = <0xf>;
607 ti,otap-del-sel-sdr50 = <0xc>;
608 ti,otap-del-sel-ddr50 = <0x9>;
609 ti,otap-del-sel-sdr104 = <0x6>;
610 ti,itap-del-sel-legacy = <0x0>;
611 ti,itap-del-sel-sd-hs = <0x0>;
612 ti,itap-del-sel-sdr12 = <0x0>;
613 ti,itap-del-sel-sdr25 = <0x0>;
619 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
625 ti,clkbuf-sel = <0x7>;
626 ti,otap-del-sel-legacy = <0x0>;
627 ti,otap-del-sel-sd-hs = <0x0>;
628 ti,otap-del-sel-sdr12 = <0xf>;
629 ti,otap-del-sel-sdr25 = <0xf>;
630 ti,otap-del-sel-sdr50 = <0xc>;
631 ti,otap-del-sel-ddr50 = <0x9>;
632 ti,otap-del-sel-sdr104 = <0x6>;
633 ti,itap-del-sel-legacy = <0x0>;
634 ti,itap-del-sel-sd-hs = <0x0>;
635 ti,itap-del-sel-sdr12 = <0x0>;
636 ti,itap-del-sel-sdr25 = <0x0>;
642 reg = <0x00 0x0f900000 0x00 0x800>,
643 <0x00 0x0f908000 0x00 0x400>;
646 ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>;
655 reg = <0x00 0x31000000 0x00 0x50000>;
656 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
657 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
669 reg = <0x00 0x0fc00000 0x00 0x70000>;
676 reg = <0x00 0x0fc40000 0x00 0x100>,
677 <0x05 0x00000000 0x01 0x00000000>;
681 cdns,trigger-address = <0x0>;
688 #size-cells = <0>;
697 reg = <0x00 0x08000000 0x00 0x200000>;
699 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
700 clocks = <&k3_clks 13 0>;
707 dmas = <&main_pktdma 0xc600 15>,
708 <&main_pktdma 0xc601 15>,
709 <&main_pktdma 0xc602 15>,
710 <&main_pktdma 0xc603 15>,
711 <&main_pktdma 0xc604 15>,
712 <&main_pktdma 0xc605 15>,
713 <&main_pktdma 0xc606 15>,
714 <&main_pktdma 0xc607 15>,
715 <&main_pktdma 0x4600 15>;
721 #size-cells = <0>;
729 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
745 reg = <0x00 0xf00 0x00 0x100>;
747 #size-cells = <0>;
748 clocks = <&k3_clks 13 0>;
756 reg = <0x00 0x3d000 0x00 0x400>;
768 reg = <0x00 0x2a000000 0x00 0x1000>;
774 reg = <0x00 0x29000000 0x00 0x200>;
784 reg = <0x00 0x29010000 0x00 0x200>;
794 reg = <0x00 0x29020000 0x00 0x200>;
804 reg = <0x00 0x29030000 0x00 0x200>;
815 reg = <0x00 0x23100000 0x00 0x100>;
817 clocks = <&k3_clks 51 0>;
825 reg = <0x00 0x23110000 0x00 0x100>;
827 clocks = <&k3_clks 52 0>;
835 reg = <0x00 0x23120000 0x00 0x100>;
837 clocks = <&k3_clks 53 0>;
844 reg = <0x00 0x23200000 0x00 0x100>;
846 clocks = <&k3_clks 59 0>;
853 reg = <0x00 0x23210000 0x00 0x100>;
855 clocks = <&k3_clks 60 0>;
862 reg = <0x00 0x23220000 0x00 0x100>;
864 clocks = <&k3_clks 62 0>;
871 reg = <0x00 0x20701000 0x00 0x200>,
872 <0x00 0x20708000 0x00 0x8000>;
880 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
886 reg = <0x00 0x20711000 0x00 0x200>,
887 <0x00 0x20718000 0x00 0x8000>;
895 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
901 reg = <0x00 0x0e000000 0x00 0x100>;
902 clocks = <&k3_clks 125 0>;
904 assigned-clocks = <&k3_clks 125 0>;
910 reg = <0x00 0x0e010000 0x00 0x100>;
911 clocks = <&k3_clks 126 0>;
913 assigned-clocks = <&k3_clks 126 0>;
919 reg = <0x00 0x0e020000 0x00 0x100>;
920 clocks = <&k3_clks 127 0>;
922 assigned-clocks = <&k3_clks 127 0>;
928 reg = <0x00 0x0e030000 0x00 0x100>;
929 clocks = <&k3_clks 128 0>;
931 assigned-clocks = <&k3_clks 128 0>;
937 reg = <0x00 0x0e0f0000 0x00 0x100>;
938 clocks = <&k3_clks 130 0>;
940 assigned-clocks = <&k3_clks 130 0>;
947 reg = <0x00 0x23000000 0x00 0x100>;
949 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
957 reg = <0x00 0x23010000 0x00 0x100>;
959 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
967 reg = <0x00 0x23020000 0x00 0x100>;
969 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
976 reg = <0x00 0x02b00000 0x00 0x2000>,
977 <0x00 0x02b08000 0x00 0x400>;
983 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
986 clocks = <&k3_clks 190 0>;
988 assigned-clocks = <&k3_clks 190 0>;
996 reg = <0x00 0x02b10000 0x00 0x2000>,
997 <0x00 0x02b18000 0x00 0x400>;
1003 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
1006 clocks = <&k3_clks 191 0>;
1008 assigned-clocks = <&k3_clks 191 0>;
1016 reg = <0x00 0x02b20000 0x00 0x2000>,
1017 <0x00 0x02b28000 0x00 0x400>;
1023 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
1026 clocks = <&k3_clks 192 0>;
1028 assigned-clocks = <&k3_clks 192 0>;
1036 reg = <0x00 0x30102000 0x00 0x1000>;
1040 dmas = <&main_bcdma_csi 0 0x5000 0>;
1047 reg = <0x00 0x30101000 0x00 0x1000>;
1048 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
1049 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
1057 #size-cells = <0>;
1059 csi0_port0: port@0 {
1060 reg = <0>;
1089 reg = <0x00 0x30110000 0x00 0x1100>;
1090 #phy-cells = <0>;
1097 reg = <0x00 0x30210000 0x00 0x10000>;