Lines Matching +full:0 +full:x23100000
11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
20 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
21 <0x01 0x00000000 0x00 0x2000>, /* GICC */
22 <0x01 0x00010000 0x00 0x1000>, /* GICH */
23 <0x01 0x00020000 0x00 0x2000>; /* GICV */
37 reg = <0x00 0x01820000 0x00 0x10000>;
38 socionext,synquacer-pre-its = <0x1000000 0x400000>;
48 ranges = <0x00 0x00 0x00100000 0x20000>;
52 reg = <0x4044 0x8>;
59 reg = <0x4130 0x4>;
65 reg = <0x82e0 0x4>;
66 clocks = <&k3_clks 157 0>;
67 assigned-clocks = <&k3_clks 157 0>;
69 #clock-cells = <0>;
74 reg = <0x82e4 0x4>;
78 #clock-cells = <0>;
87 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>;
93 reg = <0x00 0x4d000000 0x00 0x80000>,
94 <0x00 0x4a600000 0x00 0x80000>,
95 <0x00 0x4a400000 0x00 0x80000>;
105 reg = <0x00 0x48000000 0x00 0x100000>;
106 #interrupt-cells = <0>;
118 reg = <0x00 0x485c0100 0x00 0x100>,
119 <0x00 0x4c000000 0x00 0x20000>,
120 <0x00 0x4a820000 0x00 0x20000>,
121 <0x00 0x4aa40000 0x00 0x20000>,
122 <0x00 0x4bc00000 0x00 0x100000>,
123 <0x00 0x48600000 0x00 0x8000>,
124 <0x00 0x484a4000 0x00 0x2000>,
125 <0x00 0x484c2000 0x00 0x2000>,
126 <0x00 0x48420000 0x00 0x2000>;
133 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
134 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
135 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
141 reg = <0x00 0x485c0000 0x00 0x100>,
142 <0x00 0x4a800000 0x00 0x20000>,
143 <0x00 0x4aa00000 0x00 0x20000>,
144 <0x00 0x4b800000 0x00 0x200000>,
145 <0x00 0x485e0000 0x00 0x10000>,
146 <0x00 0x484a0000 0x00 0x2000>,
147 <0x00 0x484c0000 0x00 0x2000>,
148 <0x00 0x48430000 0x00 0x1000>;
157 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
158 <0x24>, /* CPSW_TX_CHAN */
159 <0x25>, /* SAUL_TX_0_CHAN */
160 <0x26>; /* SAUL_TX_1_CHAN */
161 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
162 <0x11>, /* RING_CPSW_TX_CHAN */
163 <0x12>, /* RING_SAUL_TX_0_CHAN */
164 <0x13>; /* RING_SAUL_TX_1_CHAN */
165 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
166 <0x2b>, /* CPSW_RX_CHAN */
167 <0x2d>, /* SAUL_RX_0_CHAN */
168 <0x2f>, /* SAUL_RX_1_CHAN */
169 <0x31>, /* SAUL_RX_2_CHAN */
170 <0x33>; /* SAUL_RX_3_CHAN */
171 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
172 <0x2c>, /* FLOW_CPSW_RX_CHAN */
173 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
174 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
183 ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x300000>;
189 reg = <0x00 0x4e0a0000 0x00 0x8000>;
190 #interrupt-cells = <0>;
196 ti,interrupt-ranges = <0 237 8>;
203 reg = <0x00 0x4e230000 0x00 0x100>,
204 <0x00 0x4e180000 0x00 0x8000>,
205 <0x00 0x4e100000 0x00 0x10000>;
211 ti,sci-rm-range-rchan = <0x21>;
218 reg = <0x00 0x44043000 0x00 0xfe0>;
246 reg = <0x00 0x40900000 0x00 0x1200>;
247 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
248 <&main_pktdma 0x7507 0>;
256 reg = <0x00 0x43600000 0x00 0x10000>,
257 <0x00 0x44880000 0x00 0x20000>,
258 <0x00 0x44860000 0x00 0x20000>;
270 reg = <0x00 0xf4000 0x00 0x2ac>;
273 pinctrl-single,function-mask = <0xffffffff>;
278 reg = <0x0 0x420000 0x0 0x1000>;
286 reg = <0x00 0x2400000 0x00 0x400>;
299 reg = <0x00 0x2410000 0x00 0x400>;
311 reg = <0x00 0x2420000 0x00 0x400>;
323 reg = <0x00 0x2430000 0x00 0x400>;
335 reg = <0x00 0x2440000 0x00 0x400>;
347 reg = <0x00 0x2450000 0x00 0x400>;
359 reg = <0x00 0x2460000 0x00 0x400>;
371 reg = <0x00 0x2470000 0x00 0x400>;
383 reg = <0x00 0x02800000 0x00 0x100>;
386 clocks = <&k3_clks 146 0>;
393 reg = <0x00 0x02810000 0x00 0x100>;
396 clocks = <&k3_clks 152 0>;
403 reg = <0x00 0x02820000 0x00 0x100>;
406 clocks = <&k3_clks 153 0>;
413 reg = <0x00 0x02830000 0x00 0x100>;
416 clocks = <&k3_clks 154 0>;
423 reg = <0x00 0x02840000 0x00 0x100>;
426 clocks = <&k3_clks 155 0>;
433 reg = <0x00 0x02850000 0x00 0x100>;
436 clocks = <&k3_clks 156 0>;
443 reg = <0x00 0x02860000 0x00 0x100>;
446 clocks = <&k3_clks 158 0>;
453 reg = <0x00 0x20000000 0x00 0x100>;
456 #size-cells = <0>;
465 reg = <0x00 0x20010000 0x00 0x100>;
468 #size-cells = <0>;
477 reg = <0x00 0x20020000 0x00 0x100>;
480 #size-cells = <0>;
489 reg = <0x00 0x20030000 0x00 0x100>;
492 #size-cells = <0>;
501 reg = <0x00 0x20100000 0x00 0x400>;
504 #size-cells = <0>;
506 clocks = <&k3_clks 141 0>;
512 reg = <0x00 0x20110000 0x00 0x400>;
515 #size-cells = <0>;
517 clocks = <&k3_clks 142 0>;
523 reg = <0x00 0x20120000 0x00 0x400>;
526 #size-cells = <0>;
528 clocks = <&k3_clks 143 0>;
534 reg = <0x00 0x00a00000 0x00 0x800>;
541 ti,interrupt-ranges = <0 32 16>;
547 reg = <0x00 0x00600000 0x0 0x100>;
556 ti,davinci-gpio-unbanked = <0>;
558 clocks = <&k3_clks 77 0>;
565 reg = <0x00 0x00601000 0x0 0x100>;
574 ti,davinci-gpio-unbanked = <0>;
576 clocks = <&k3_clks 78 0>;
583 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
590 ti,clkbuf-sel = <0x7>;
591 ti,otap-del-sel-legacy = <0x0>;
592 ti,otap-del-sel-mmc-hs = <0x0>;
593 ti,otap-del-sel-hs200 = <0x6>;
599 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
605 ti,clkbuf-sel = <0x7>;
606 ti,otap-del-sel-legacy = <0x0>;
607 ti,otap-del-sel-sd-hs = <0x0>;
608 ti,otap-del-sel-sdr12 = <0xf>;
609 ti,otap-del-sel-sdr25 = <0xf>;
610 ti,otap-del-sel-sdr50 = <0xc>;
611 ti,otap-del-sel-sdr104 = <0x6>;
612 ti,otap-del-sel-ddr50 = <0x9>;
613 ti,itap-del-sel-legacy = <0x0>;
614 ti,itap-del-sel-sd-hs = <0x0>;
615 ti,itap-del-sel-sdr12 = <0x0>;
616 ti,itap-del-sel-sdr25 = <0x0>;
622 reg = <0x00 0xfa20000 0x00 0x260>, <0x00 0xfa28000 0x00 0x134>;
628 ti,clkbuf-sel = <0x7>;
629 ti,otap-del-sel-legacy = <0x0>;
630 ti,otap-del-sel-sd-hs = <0x0>;
631 ti,otap-del-sel-sdr12 = <0xf>;
632 ti,otap-del-sel-sdr25 = <0xf>;
633 ti,otap-del-sel-sdr50 = <0xc>;
634 ti,otap-del-sel-sdr104 = <0x6>;
635 ti,otap-del-sel-ddr50 = <0x9>;
636 ti,itap-del-sel-legacy = <0x0>;
637 ti,itap-del-sel-sd-hs = <0x0>;
638 ti,itap-del-sel-sdr12 = <0x0>;
639 ti,itap-del-sel-sdr25 = <0x0>;
645 reg = <0x00 0x0f900000 0x00 0x800>,
646 <0x00 0x0f908000 0x00 0x400>;
649 ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>;
658 reg = <0x00 0x31000000 0x00 0x50000>;
659 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
660 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
672 reg = <0x00 0x0f910000 0x00 0x800>,
673 <0x00 0x0f918000 0x00 0x400>;
676 ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>;
685 reg = <0x00 0x31100000 0x00 0x50000>;
686 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
687 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
698 reg = <0x00 0x0fc00000 0x00 0x70000>;
706 reg = <0x00 0x0fc40000 0x00 0x100>,
707 <0x05 0x00000000 0x01 0x00000000>;
711 cdns,trigger-address = <0x0>;
718 #size-cells = <0>;
726 reg = <0x0 0x8000000 0x0 0x200000>;
728 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
729 clocks = <&k3_clks 13 0>;
736 dmas = <&main_pktdma 0xc600 15>,
737 <&main_pktdma 0xc601 15>,
738 <&main_pktdma 0xc602 15>,
739 <&main_pktdma 0xc603 15>,
740 <&main_pktdma 0xc604 15>,
741 <&main_pktdma 0xc605 15>,
742 <&main_pktdma 0xc606 15>,
743 <&main_pktdma 0xc607 15>,
744 <&main_pktdma 0x4600 15>;
750 #size-cells = <0>;
758 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
773 reg = <0x0 0xf00 0x0 0x100>;
775 #size-cells = <0>;
776 clocks = <&k3_clks 13 0>;
784 reg = <0x0 0x3d000 0x0 0x400>;
796 reg = <0x00 0x2a000000 0x00 0x1000>;
802 reg = <0x00 0x29000000 0x00 0x200>;
811 reg = <0x00 0x29010000 0x00 0x200>;
820 reg = <0x00 0x29020000 0x00 0x200>;
829 reg = <0x00 0x29030000 0x00 0x200>;
838 reg = <0x00 0x20701000 0x00 0x200>,
839 <0x00 0x20708000 0x00 0x8000>;
847 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
853 reg = <0x00 0x0e000000 0x00 0x100>;
854 clocks = <&k3_clks 125 0>;
856 assigned-clocks = <&k3_clks 125 0>;
862 reg = <0x00 0x0e010000 0x00 0x100>;
863 clocks = <&k3_clks 126 0>;
865 assigned-clocks = <&k3_clks 126 0>;
871 reg = <0x00 0x0e020000 0x00 0x100>;
872 clocks = <&k3_clks 127 0>;
874 assigned-clocks = <&k3_clks 127 0>;
880 reg = <0x00 0x0e030000 0x00 0x100>;
881 clocks = <&k3_clks 128 0>;
883 assigned-clocks = <&k3_clks 128 0>;
889 reg = <0x00 0x0e040000 0x00 0x100>;
890 clocks = <&k3_clks 205 0>;
892 assigned-clocks = <&k3_clks 205 0>;
899 reg = <0x00 0x23000000 0x00 0x100>;
901 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
909 reg = <0x00 0x23010000 0x00 0x100>;
911 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
919 reg = <0x00 0x23020000 0x00 0x100>;
921 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
929 reg = <0x00 0x23100000 0x00 0x100>;
931 clocks = <&k3_clks 51 0>;
939 reg = <0x00 0x23110000 0x00 0x100>;
941 clocks = <&k3_clks 52 0>;
949 reg = <0x00 0x23120000 0x00 0x100>;
951 clocks = <&k3_clks 53 0>;
958 reg = <0x00 0x23200000 0x00 0x100>;
960 clocks = <&k3_clks 59 0>;
967 reg = <0x00 0x23210000 0x00 0x100>;
969 clocks = <&k3_clks 60 0>;
976 reg = <0x00 0x23220000 0x00 0x100>;
978 clocks = <&k3_clks 62 0>;
985 reg = <0x00 0x02b00000 0x00 0x2000>,
986 <0x00 0x02b08000 0x00 0x400>;
992 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
995 clocks = <&k3_clks 190 0>;
997 assigned-clocks = <&k3_clks 190 0>;
1005 reg = <0x00 0x02b10000 0x00 0x2000>,
1006 <0x00 0x02b18000 0x00 0x400>;
1012 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
1015 clocks = <&k3_clks 191 0>;
1017 assigned-clocks = <&k3_clks 191 0>;
1025 reg = <0x00 0x02b20000 0x00 0x2000>,
1026 <0x00 0x02b28000 0x00 0x400>;
1032 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
1035 clocks = <&k3_clks 192 0>;
1037 assigned-clocks = <&k3_clks 192 0>;
1045 dmas = <&main_bcdma_csi 0 0x5000 0>;
1047 reg = <0x00 0x30102000 0x00 0x1000>;
1056 reg = <0x00 0x30101000 0x00 0x1000>;
1057 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
1058 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
1066 #size-cells = <0>;
1068 csi0_port0: port@0 {
1069 reg = <0>;
1098 reg = <0x00 0x30110000 0x00 0x1100>;
1099 #phy-cells = <0>;
1106 reg = <0x00 0x30200000 0x00 0x1000>, /* common */
1107 <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
1108 <0x00 0x30206000 0x00 0x1000>, /* vid */
1109 <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
1110 <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
1111 <0x00 0x3020a000 0x00 0x1000>, /* vp1: Tied OFF in the SoC */
1112 <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */
1113 <0x00 0x30201000 0x00 0x1000>; /* common1 */
1118 <&k3_clks 186 0>,
1126 #size-cells = <0>;
1132 reg = <0x00 0x30210000 0x00 0x10000>;
1139 reg = <0x00 0x7e000000 0x00 0x00100000>;
1145 ti,sci-proc-ids = <0x04 0xff>;
1151 reg = <0x00 0xfd20000 0x00 0x100>,
1152 <0x00 0xfd20200 0x00 0x200>;
1154 clocks = <&k3_clks 201 0>;