Lines Matching +full:0 +full:xfe820000
11 cpu0_opp_table: opp-table-0 {
101 reg = <0 0xfc000000 0 0x1000>;
108 ports-implemented = <0x1>;
115 reg = <0x0 0xfdc70000 0x0 0x1000>;
120 reg = <0x0 0xfe190080 0x0 0x20>;
125 reg = <0x0 0xfe190100 0x0 0x20>;
130 reg = <0x0 0xfe190200 0x0 0x20>;
135 reg = <0x0 0xfdcb8000 0x0 0x10000>;
140 reg = <0x0 0xfe8c0000 0x0 0x20000>;
141 #phy-cells = <0>;
155 bus-range = <0x10 0x1f>;
169 interrupt-map-mask = <0 0 0 7>;
170 interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
171 <0 0 0 2 &pcie3x1_intc 1>,
172 <0 0 0 3 &pcie3x1_intc 2>,
173 <0 0 0 4 &pcie3x1_intc 3>;
178 msi-map = <0x1000 &its 0x1000 0x1000>;
183 reg = <0x3 0xc0400000 0x0 0x00400000>,
184 <0x0 0xfe270000 0x0 0x00010000>,
185 <0x0 0xf2000000 0x0 0x00100000>;
186 ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
187 <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>,
188 <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>;
197 #address-cells = <0>;
208 bus-range = <0x20 0x2f>;
222 interrupt-map-mask = <0 0 0 7>;
223 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
224 <0 0 0 2 &pcie3x2_intc 1>,
225 <0 0 0 3 &pcie3x2_intc 2>,
226 <0 0 0 4 &pcie3x2_intc 3>;
231 msi-map = <0x2000 &its 0x2000 0x1000>;
236 reg = <0x3 0xc0800000 0x0 0x00400000>,
237 <0x0 0xfe280000 0x0 0x00010000>,
238 <0x0 0xf0000000 0x0 0x00100000>;
239 ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
240 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>,
241 <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>;
250 #address-cells = <0>;
259 reg = <0x0 0xfe2a0000 0x0 0x10000>;
283 #address-cells = <0x1>;
284 #size-cells = <0x0>;
288 snps,blen = <0 0 0 0 16 8 4>;
306 reg = <0x0 0xfe570000 0x0 0x1000>;
313 pinctrl-0 = <&can0m0_pins>;
319 reg = <0x0 0xfe580000 0x0 0x1000>;
326 pinctrl-0 = <&can1m0_pins>;
332 reg = <0x0 0xfe590000 0x0 0x1000>;
339 pinctrl-0 = <&can2m0_pins>;
345 reg = <0x0 0xfe820000 0x0 0x100>;
397 #power-domain-cells = <0>;