Lines Matching +full:0 +full:xff720000
33 #clock-cells = <0>;
40 #clock-cells = <0>;
47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0x0 0x0>;
64 reg = <0x0 0x1>;
76 reg = <0x0 0x2>;
88 reg = <0x0 0x3>;
103 arm,psci-suspend-param = <0x0010000>;
147 opp-supported-hw = <0xf9 0xffff>;
211 arm,smc-id = <0x82000010>;
213 #size-cells = <0>;
216 reg = <0x14>;
231 reg = <0x0 0xff260000 0x0 0x100>;
234 gpio-ranges = <&pinctrl 0 0 32>;
235 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
243 reg = <0x0 0xff620000 0x0 0x100>;
246 gpio-ranges = <&pinctrl 0 32 32>;
255 reg = <0x0 0xff630000 0x0 0x100>;
258 gpio-ranges = <&pinctrl 0 64 32>;
267 reg = <0x0 0xffac0000 0x0 0x100>;
270 gpio-ranges = <&pinctrl 0 96 32>;
279 reg = <0x0 0xffad0000 0x0 0x100>;
282 gpio-ranges = <&pinctrl 0 128 32>;
302 reg = <0x0 0x0010f000 0x0 0x100>;
323 reg = <0x0 0xfe000000 0x0 0x400000>,
324 <0x0 0xff500000 0x0 0x10000>,
325 <0x0 0xfc000000 0x0 0x100000>;
327 bus-range = <0x0 0xff>;
342 interrupt-map-mask = <0 0 0 7>;
343 interrupt-map = <0 0 0 1 &pcie2x1_intc 0>,
344 <0 0 0 2 &pcie2x1_intc 1>,
345 <0 0 0 3 &pcie2x1_intc 2>,
346 <0 0 0 4 &pcie2x1_intc 3>;
347 linux,pci-domain = <0>;
356 ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000
357 0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000
358 0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;
367 #address-cells = <0>;
377 #address-cells = <0>;
379 reg = <0x0 0xfe901000 0 0x1000>,
380 <0x0 0xfe902000 0 0x2000>,
381 <0x0 0xfe904000 0 0x2000>,
382 <0x0 0xfe906000 0 0x2000>;
388 reg = <0x0 0xfee03800 0x0 0x20>;
393 reg = <0x0 0xfee10000 0x0 0x20>;
398 reg = <0x0 0xfee10100 0x0 0x20>;
403 reg = <0x0 0xfee10200 0x0 0x20>;
408 reg = <0x0 0xfee10300 0x0 0x20>;
413 reg = <0x0 0xfee10400 0x0 0x20>;
418 reg = <0x0 0xfee20000 0x0 0x20>;
423 reg = <0x0 0xfee30000 0x0 0x20>;
428 reg = <0x0 0xfee40000 0x0 0x20>;
433 reg = <0x0 0xfee50000 0x0 0x20>;
438 reg = <0x0 0xfee60000 0x0 0x20>;
443 reg = <0x0 0xfee70000 0x0 0x20>;
448 reg = <0x0 0xfee70100 0x0 0x20>;
453 reg = <0x0 0xfee80000 0x0 0x20>;
458 reg = <0x0 0xfee90000 0x0 0x20>;
463 reg = <0x0 0xfee90100 0x0 0x20>;
468 reg = <0x0 0xfee90200 0x0 0x20>;
473 reg = <0x0 0xfeea0000 0x0 0x20>;
478 reg = <0x0 0xfeea0100 0x0 0x20>;
483 reg = <0x0 0xfeeb0000 0x0 0x20>;
488 reg = <0x0 0xfeeb0100 0x0 0x20>;
493 reg = <0x0 0xfeeb0200 0x0 0x20>;
498 reg = <0x0 0xfeeb0300 0x0 0x20>;
503 reg = <0x0 0xfeeb0400 0x0 0x20>;
508 reg = <0x0 0xfeeb0500 0x0 0x20>;
513 reg = <0x0 0xfeeb0600 0x0 0x20>;
518 reg = <0x0 0xfeeb0700 0x0 0x20>;
523 reg = <0x0 0xfeeb0800 0x0 0x20>;
528 reg = <0x0 0xff010000 0x0 0x10000>;
532 offset = <0x220>;
542 reg = <0x0 0xff030000 0x0 0x10000>;
547 reg = <0x0 0xff040000 0x0 0x10000>;
552 reg = <0x0 0xff060000 0x0 0x30000>;
557 reg = <0x0 0xff090000 0x0 0x8000>;
562 reg = <0x0 0xff098000 0x0 0x8000>;
567 reg = <0x0 0xff100000 0x0 0x40000>;
579 reg = <0x0 0xff200000 0x0 0x1000>;
584 pinctrl-0 = <&i2c0_xfer>;
586 #size-cells = <0>;
592 reg = <0x0 0xff210000 0x0 0x100>;
603 reg = <0x0 0xff220000 0x0 0x1000>;
611 pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>;
613 #size-cells = <0>;
619 reg = <0x0 0xff230000 0x0 0x10>;
623 pinctrl-0 = <&pwm0m0_pins>;
630 reg = <0x0 0xff230010 0x0 0x10>;
634 pinctrl-0 = <&pwm1m0_pins>;
641 reg = <0x0 0xff230020 0x0 0x10>;
645 pinctrl-0 = <&pwm2m0_pins>;
652 reg = <0x0 0xff230030 0x0 0x10>;
656 pinctrl-0 = <&pwm3m0_pins>;
663 reg = <0x0 0xff258000 0x0 0x1000>;
669 #size-cells = <0>;
674 #power-domain-cells = <0>;
680 #power-domain-cells = <0>;
686 #power-domain-cells = <0>;
695 #size-cells = <0>;
700 #power-domain-cells = <0>;
709 #size-cells = <0>;
716 #power-domain-cells = <0>;
724 #power-domain-cells = <0>;
731 reg = <0x0 0xff320000 0x0 0x4000>;
748 reg = <0x0 0xff640000 0x0 0x1000>;
756 pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>;
758 #size-cells = <0>;
764 reg = <0x0 0xff650000 0x0 0x1000>;
772 pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>;
774 #size-cells = <0>;
780 reg = <0x0 0xff670000 0x0 0x100>;
791 reg = <0x0 0xff680000 0x0 0x100>;
802 reg = <0x0 0xff690000 0x0 0x100>;
813 reg = <0x0 0xff6a0000 0x0 0x100>;
824 reg = <0x0 0xff6b0000 0x0 0x100>;
835 reg = <0x0 0xff6c0000 0x0 0x100>;
846 reg = <0x0 0xff6d0000 0x0 0x100>;
857 reg = <0x0 0xff6e0000 0x0 0x100>;
868 reg = <0x0 0xff6f0000 0x0 0x100>;
879 reg = <0x0 0xff700000 0x0 0x10>;
883 pinctrl-0 = <&pwm4m0_pins>;
890 reg = <0x0 0xff700010 0x0 0x10>;
894 pinctrl-0 = <&pwm5m0_pins>;
901 reg = <0x0 0xff700020 0x0 0x10>;
905 pinctrl-0 = <&pwm6m0_pins>;
912 reg = <0x0 0xff700030 0x0 0x10>;
916 pinctrl-0 = <&pwm7m0_pins>;
923 reg = <0x0 0xff710000 0x0 0x10>;
927 pinctrl-0 = <&pwm8m0_pins>;
934 reg = <0x0 0xff710010 0x0 0x10>;
938 pinctrl-0 = <&pwm9m0_pins>;
945 reg = <0x0 0xff710020 0x0 0x10>;
949 pinctrl-0 = <&pwm10m0_pins>;
956 reg = <0x0 0xff710030 0x0 0x10>;
960 pinctrl-0 = <&pwm11m0_pins>;
967 reg = <0x0 0xff720000 0x0 0x10>;
971 pinctrl-0 = <&pwm12m0_pins>;
978 reg = <0x0 0xff720010 0x0 0x10>;
982 pinctrl-0 = <&pwm13m0_pins>;
989 reg = <0x0 0xff720020 0x0 0x10>;
993 pinctrl-0 = <&pwm14m0_pins>;
1000 reg = <0x0 0xff720030 0x0 0x10>;
1004 pinctrl-0 = <&pwm15m0_pins>;
1011 reg = <0x0 0xff730000 0x0 0x100>;
1023 reg = <0x0 0xff750000 0x0 0x100>;
1039 reg = <0x0 0xff860000 0x0 0x10000>;
1044 #size-cells = <0>;
1050 reg = <0x0 0xff870000 0x0 0x10000>;
1069 reg = <0x0 0xff880000 0x0 0x10000>;
1074 fifo-depth = <0x100>;
1084 reg = <0x0 0xff890000 0x0 0x10000>;
1089 fifo-depth = <0x100>;
1098 reg = <0x0 0xff990000 0x0 0x4000>;
1109 reg = <0x0 0xffa00000 0x0 0x1000>;
1114 pinctrl-0 = <&i2c1m0_xfer>;
1116 #size-cells = <0>;
1122 reg = <0x0 0xffa10000 0x0 0x1000>;
1127 pinctrl-0 = <&i2c2m0_xfer>;
1129 #size-cells = <0>;
1135 reg = <0x0 0xffa20000 0x0 0x1000>;
1140 pinctrl-0 = <&i2c3m0_xfer>;
1142 #size-cells = <0>;
1148 reg = <0x0 0xffa30000 0x0 0x1000>;
1153 pinctrl-0 = <&i2c4m0_xfer>;
1155 #size-cells = <0>;
1161 reg = <0x0 0xffa40000 0x0 0x1000>;
1166 pinctrl-0 = <&i2c5m0_xfer>;
1168 #size-cells = <0>;
1174 reg = <0x0 0xffaa0000 0x0 0x100>;