Lines Matching +full:r9a09g057 +full:- +full:gbeth
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "renesas,r9a09g057";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_extal_clk: audio-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
30 cluster0_opp: opp-table-0 {
31 compatible = "operating-points-v2";
33 opp-1700000000 {
34 opp-hz = /bits/ 64 <1700000000>;
35 opp-microvolt = <900000>;
36 clock-latency-ns = <300000>;
38 opp-850000000 {
39 opp-hz = /bits/ 64 <850000000>;
40 opp-microvolt = <800000>;
41 clock-latency-ns = <300000>;
43 opp-425000000 {
44 opp-hz = /bits/ 64 <425000000>;
45 opp-microvolt = <800000>;
46 clock-latency-ns = <300000>;
48 opp-212500000 {
49 opp-hz = /bits/ 64 <212500000>;
50 opp-microvolt = <800000>;
51 clock-latency-ns = <300000>;
52 opp-suspend;
57 #address-cells = <1>;
58 #size-cells = <0>;
61 compatible = "arm,cortex-a55";
64 next-level-cache = <&L3_CA55>;
65 enable-method = "psci";
67 operating-points-v2 = <&cluster0_opp>;
71 compatible = "arm,cortex-a55";
74 next-level-cache = <&L3_CA55>;
75 enable-method = "psci";
77 operating-points-v2 = <&cluster0_opp>;
81 compatible = "arm,cortex-a55";
84 next-level-cache = <&L3_CA55>;
85 enable-method = "psci";
87 operating-points-v2 = <&cluster0_opp>;
91 compatible = "arm,cortex-a55";
94 next-level-cache = <&L3_CA55>;
95 enable-method = "psci";
97 operating-points-v2 = <&cluster0_opp>;
100 L3_CA55: cache-controller-0 {
102 cache-unified;
103 cache-size = <0x100000>;
104 cache-level = <3>;
108 gpu_opp_table: opp-table-1 {
109 compatible = "operating-points-v2";
111 opp-630000000 {
112 opp-hz = /bits/ 64 <630000000>;
113 opp-microvolt = <800000>;
116 opp-315000000 {
117 opp-hz = /bits/ 64 <315000000>;
118 opp-microvolt = <800000>;
121 opp-157500000 {
122 opp-hz = /bits/ 64 <157500000>;
123 opp-microvolt = <800000>;
126 opp-78750000 {
127 opp-hz = /bits/ 64 <78750000>;
128 opp-microvolt = <800000>;
131 opp-19687500 {
132 opp-hz = /bits/ 64 <19687500>;
133 opp-microvolt = <800000>;
138 compatible = "arm,psci-1.0", "arm,psci-0.2";
142 qextal_clk: qextal-clk {
143 compatible = "fixed-clock";
144 #clock-cells = <0>;
146 clock-frequency = <0>;
149 rtxin_clk: rtxin-clk {
150 compatible = "fixed-clock";
151 #clock-cells = <0>;
153 clock-frequency = <0>;
157 compatible = "simple-bus";
158 interrupt-parent = <&gic>;
159 #address-cells = <2>;
160 #size-cells = <2>;
163 icu: interrupt-controller@10400000 {
164 compatible = "renesas,r9a09g057-icu";
166 #interrupt-cells = <2>;
167 #address-cells = <0>;
168 interrupt-controller;
227 interrupt-names = "nmi",
242 "int-ca55-0", "int-ca55-1",
243 "int-ca55-2", "int-ca55-3",
244 "icu-error-ca55",
245 "gpt-u0-gtciada", "gpt-u0-gtciadb",
246 "gpt-u1-gtciada", "gpt-u1-gtciadb";
248 power-domains = <&cpg>;
253 compatible = "renesas,r9a09g057-pinctrl";
256 gpio-controller;
257 #gpio-cells = <2>;
258 gpio-ranges = <&pinctrl 0 0 96>;
259 #interrupt-cells = <2>;
260 interrupt-controller;
261 interrupt-parent = <&icu>;
262 power-domains = <&cpg>;
266 cpg: clock-controller@10420000 {
267 compatible = "renesas,r9a09g057-cpg";
270 clock-names = "audio_extal", "rtxin", "qextal";
271 #clock-cells = <2>;
272 #reset-cells = <1>;
273 #power-domain-cells = <0>;
276 sys: system-controller@10430000 {
277 compatible = "renesas,r9a09g057-sys";
284 compatible = "renesas,r9a09g057-xspi", "renesas,r9a09g047-xspi";
287 reg-names = "regs", "dirmap";
290 interrupt-names = "pulse", "err_pulse";
295 clock-names = "ahb", "axi", "spi", "spix2";
297 reset-names = "hresetn", "aresetn";
298 power-domains = <&cpg>;
299 #address-cells = <1>;
300 #size-cells = <0>;
304 dmac0: dma-controller@11400000 {
305 compatible = "renesas,r9a09g057-dmac";
324 interrupt-names = "error",
330 power-domains = <&cpg>;
332 #dma-cells = <1>;
333 dma-channels = <16>;
337 dmac1: dma-controller@14830000 {
338 compatible = "renesas,r9a09g057-dmac";
357 interrupt-names = "error",
363 power-domains = <&cpg>;
365 #dma-cells = <1>;
366 dma-channels = <16>;
370 dmac2: dma-controller@14840000 {
371 compatible = "renesas,r9a09g057-dmac";
390 interrupt-names = "error",
396 power-domains = <&cpg>;
398 #dma-cells = <1>;
399 dma-channels = <16>;
403 dmac3: dma-controller@12000000 {
404 compatible = "renesas,r9a09g057-dmac";
423 interrupt-names = "error",
429 power-domains = <&cpg>;
431 #dma-cells = <1>;
432 dma-channels = <16>;
436 dmac4: dma-controller@12010000 {
437 compatible = "renesas,r9a09g057-dmac";
456 interrupt-names = "error",
462 power-domains = <&cpg>;
464 #dma-cells = <1>;
465 dma-channels = <16>;
470 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
475 power-domains = <&cpg>;
480 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
485 power-domains = <&cpg>;
490 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
495 power-domains = <&cpg>;
500 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
505 power-domains = <&cpg>;
510 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
515 power-domains = <&cpg>;
520 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
525 power-domains = <&cpg>;
530 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
535 power-domains = <&cpg>;
540 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
545 power-domains = <&cpg>;
550 compatible = "renesas,r9a09g057-wdt";
553 clock-names = "pclk", "oscclk";
555 power-domains = <&cpg>;
560 compatible = "renesas,r9a09g057-wdt";
563 clock-names = "pclk", "oscclk";
565 power-domains = <&cpg>;
570 compatible = "renesas,r9a09g057-wdt";
573 clock-names = "pclk", "oscclk";
575 power-domains = <&cpg>;
580 compatible = "renesas,r9a09g057-wdt";
583 clock-names = "pclk", "oscclk";
585 power-domains = <&cpg>;
590 compatible = "renesas,scif-r9a09g057";
601 interrupt-names = "eri", "rxi", "txi", "bri", "dri",
602 "tei", "tei-dri", "rxi-edge", "txi-edge";
604 clock-names = "fck";
605 power-domains = <&cpg>;
611 compatible = "renesas,riic-r9a09g057";
621 interrupt-names = "tei", "ri", "ti", "spi", "sti",
625 power-domains = <&cpg>;
626 #address-cells = <1>;
627 #size-cells = <0>;
632 compatible = "renesas,riic-r9a09g057";
642 interrupt-names = "tei", "ri", "ti", "spi", "sti",
646 power-domains = <&cpg>;
647 #address-cells = <1>;
648 #size-cells = <0>;
653 compatible = "renesas,riic-r9a09g057";
663 interrupt-names = "tei", "ri", "ti", "spi", "sti",
667 power-domains = <&cpg>;
668 #address-cells = <1>;
669 #size-cells = <0>;
674 compatible = "renesas,riic-r9a09g057";
684 interrupt-names = "tei", "ri", "ti", "spi", "sti",
688 power-domains = <&cpg>;
689 #address-cells = <1>;
690 #size-cells = <0>;
695 compatible = "renesas,riic-r9a09g057";
705 interrupt-names = "tei", "ri", "ti", "spi", "sti",
709 power-domains = <&cpg>;
710 #address-cells = <1>;
711 #size-cells = <0>;
716 compatible = "renesas,riic-r9a09g057";
726 interrupt-names = "tei", "ri", "ti", "spi", "sti",
730 power-domains = <&cpg>;
731 #address-cells = <1>;
732 #size-cells = <0>;
737 compatible = "renesas,riic-r9a09g057";
747 interrupt-names = "tei", "ri", "ti", "spi", "sti",
751 power-domains = <&cpg>;
752 #address-cells = <1>;
753 #size-cells = <0>;
758 compatible = "renesas,riic-r9a09g057";
768 interrupt-names = "tei", "ri", "ti", "spi", "sti",
772 power-domains = <&cpg>;
773 #address-cells = <1>;
774 #size-cells = <0>;
779 compatible = "renesas,riic-r9a09g057";
789 interrupt-names = "tei", "ri", "ti", "spi", "sti",
793 power-domains = <&cpg>;
794 #address-cells = <1>;
795 #size-cells = <0>;
800 compatible = "renesas,r9a09g057-mali",
801 "arm,mali-bifrost";
807 interrupt-names = "job", "mmu", "gpu", "event";
811 clock-names = "gpu", "bus", "bus_ace";
812 power-domains = <&cpg>;
816 reset-names = "rst", "axi_rst", "ace_rst";
817 operating-points-v2 = <&gpu_opp_table>;
821 gic: interrupt-controller@14900000 {
822 compatible = "arm,gic-v3";
825 #interrupt-cells = <3>;
826 #address-cells = <0>;
827 interrupt-controller;
832 compatible = "generic-ohci";
838 phy-names = "usb";
839 power-domains = <&cpg>;
844 compatible = "generic-ohci";
850 phy-names = "usb";
851 power-domains = <&cpg>;
856 compatible = "generic-ehci";
862 phy-names = "usb";
864 power-domains = <&cpg>;
869 compatible = "generic-ehci";
875 phy-names = "usb";
877 power-domains = <&cpg>;
881 usb2_phy0: usb-phy@15800200 {
882 compatible = "renesas,usb2-phy-r9a09g057";
887 clock-names = "fck", "usb_x1";
889 #phy-cells = <1>;
890 power-domains = <&cpg>;
894 usb2_phy1: usb-phy@15810200 {
895 compatible = "renesas,usb2-phy-r9a09g057";
900 clock-names = "fck", "usb_x1";
902 #phy-cells = <1>;
903 power-domains = <&cpg>;
908 compatible = "renesas,usbhs-r9a09g057",
909 "renesas,rzg2l-usbhs";
919 phy-names = "usb";
920 power-domains = <&cpg>;
924 usb20phyrst: usb20phy-reset@15830000 {
925 compatible = "renesas,r9a09g057-usb2phy-reset";
929 power-domains = <&cpg>;
930 #reset-cells = <0>;
934 usb21phyrst: usb21phy-reset@15840000 {
935 compatible = "renesas,r9a09g057-usb2phy-reset";
939 power-domains = <&cpg>;
940 #reset-cells = <0>;
945 compatible = "renesas,sdhi-r9a09g057";
951 clock-names = "core", "clkh", "cd", "aclk";
953 power-domains = <&cpg>;
956 sdhi0_vqmmc: vqmmc-regulator {
957 regulator-name = "SDHI0-VQMMC";
958 regulator-min-microvolt = <1800000>;
959 regulator-max-microvolt = <3300000>;
965 compatible = "renesas,sdhi-r9a09g057";
971 clock-names = "core", "clkh", "cd", "aclk";
973 power-domains = <&cpg>;
976 sdhi1_vqmmc: vqmmc-regulator {
977 regulator-name = "SDHI1-VQMMC";
978 regulator-min-microvolt = <1800000>;
979 regulator-max-microvolt = <3300000>;
985 compatible = "renesas,sdhi-r9a09g057";
991 clock-names = "core", "clkh", "cd", "aclk";
993 power-domains = <&cpg>;
996 sdhi2_vqmmc: vqmmc-regulator {
997 regulator-name = "SDHI2-VQMMC";
998 regulator-min-microvolt = <1800000>;
999 regulator-max-microvolt = <3300000>;
1005 compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth",
1006 "snps,dwmac-5.20";
1019 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
1020 "rx-queue-0", "rx-queue-1", "rx-queue-2",
1021 "rx-queue-3", "tx-queue-0", "tx-queue-1",
1022 "tx-queue-2", "tx-queue-3";
1027 clock-names = "stmmaceth", "pclk", "ptp_ref",
1028 "tx", "rx", "tx-180", "rx-180";
1030 power-domains = <&cpg>;
1031 snps,multicast-filter-bins = <256>;
1032 snps,perfect-filter-entries = <128>;
1033 rx-fifo-depth = <8192>;
1034 tx-fifo-depth = <8192>;
1035 snps,fixed-burst;
1036 snps,no-pbl-x8;
1038 snps,axi-config = <&stmmac_axi_setup>;
1039 snps,mtl-rx-config = <&mtl_rx_setup0>;
1040 snps,mtl-tx-config = <&mtl_tx_setup0>;
1046 compatible = "snps,dwmac-mdio";
1047 #address-cells = <1>;
1048 #size-cells = <0>;
1051 mtl_rx_setup0: rx-queues-config {
1052 snps,rx-queues-to-use = <4>;
1053 snps,rx-sched-sp;
1056 snps,dcb-algorithm;
1058 snps,map-to-dma-channel = <0>;
1062 snps,dcb-algorithm;
1064 snps,map-to-dma-channel = <1>;
1068 snps,dcb-algorithm;
1070 snps,map-to-dma-channel = <2>;
1074 snps,dcb-algorithm;
1076 snps,map-to-dma-channel = <3>;
1080 mtl_tx_setup0: tx-queues-config {
1081 snps,tx-queues-to-use = <4>;
1084 snps,dcb-algorithm;
1089 snps,dcb-algorithm;
1094 snps,dcb-algorithm;
1099 snps,dcb-algorithm;
1106 compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth",
1107 "snps,dwmac-5.20";
1120 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
1121 "rx-queue-0", "rx-queue-1", "rx-queue-2",
1122 "rx-queue-3", "tx-queue-0", "tx-queue-1",
1123 "tx-queue-2", "tx-queue-3";
1128 clock-names = "stmmaceth", "pclk", "ptp_ref",
1129 "tx", "rx", "tx-180", "rx-180";
1131 power-domains = <&cpg>;
1132 snps,multicast-filter-bins = <256>;
1133 snps,perfect-filter-entries = <128>;
1134 rx-fifo-depth = <8192>;
1135 tx-fifo-depth = <8192>;
1136 snps,fixed-burst;
1137 snps,no-pbl-x8;
1139 snps,axi-config = <&stmmac_axi_setup>;
1140 snps,mtl-rx-config = <&mtl_rx_setup1>;
1141 snps,mtl-tx-config = <&mtl_tx_setup1>;
1147 compatible = "snps,dwmac-mdio";
1148 #address-cells = <1>;
1149 #size-cells = <0>;
1152 mtl_rx_setup1: rx-queues-config {
1153 snps,rx-queues-to-use = <4>;
1154 snps,rx-sched-sp;
1157 snps,dcb-algorithm;
1159 snps,map-to-dma-channel = <0>;
1163 snps,dcb-algorithm;
1165 snps,map-to-dma-channel = <1>;
1169 snps,dcb-algorithm;
1171 snps,map-to-dma-channel = <2>;
1175 snps,dcb-algorithm;
1177 snps,map-to-dma-channel = <3>;
1181 mtl_tx_setup1: tx-queues-config {
1182 snps,tx-queues-to-use = <4>;
1185 snps,dcb-algorithm;
1190 snps,dcb-algorithm;
1195 snps,dcb-algorithm;
1200 snps,dcb-algorithm;
1207 stmmac_axi_setup: stmmac-axi-config {
1215 compatible = "arm,armv8-timer";
1216 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1221 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";