Lines Matching +full:sp +full:- +full:disabled +full:- +full:ports
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_extal_clk: audio-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
30 cluster0_opp: opp-table-0 {
31 compatible = "operating-points-v2";
33 opp-1700000000 {
34 opp-hz = /bits/ 64 <1700000000>;
35 opp-microvolt = <900000>;
36 clock-latency-ns = <300000>;
38 opp-850000000 {
39 opp-hz = /bits/ 64 <850000000>;
40 opp-microvolt = <800000>;
41 clock-latency-ns = <300000>;
43 opp-425000000 {
44 opp-hz = /bits/ 64 <425000000>;
45 opp-microvolt = <800000>;
46 clock-latency-ns = <300000>;
48 opp-212500000 {
49 opp-hz = /bits/ 64 <212500000>;
50 opp-microvolt = <800000>;
51 clock-latency-ns = <300000>;
52 opp-suspend;
57 #address-cells = <1>;
58 #size-cells = <0>;
61 compatible = "arm,cortex-a55";
64 next-level-cache = <&L3_CA55>;
65 enable-method = "psci";
67 operating-points-v2 = <&cluster0_opp>;
71 compatible = "arm,cortex-a55";
74 next-level-cache = <&L3_CA55>;
75 enable-method = "psci";
77 operating-points-v2 = <&cluster0_opp>;
81 compatible = "arm,cortex-a55";
84 next-level-cache = <&L3_CA55>;
85 enable-method = "psci";
87 operating-points-v2 = <&cluster0_opp>;
91 compatible = "arm,cortex-a55";
94 next-level-cache = <&L3_CA55>;
95 enable-method = "psci";
97 operating-points-v2 = <&cluster0_opp>;
100 L3_CA55: cache-controller-0 {
102 cache-unified;
103 cache-size = <0x100000>;
104 cache-level = <3>;
108 gpu_opp_table: opp-table-1 {
109 compatible = "operating-points-v2";
111 opp-630000000 {
112 opp-hz = /bits/ 64 <630000000>;
113 opp-microvolt = <800000>;
116 opp-315000000 {
117 opp-hz = /bits/ 64 <315000000>;
118 opp-microvolt = <800000>;
121 opp-157500000 {
122 opp-hz = /bits/ 64 <157500000>;
123 opp-microvolt = <800000>;
126 opp-78750000 {
127 opp-hz = /bits/ 64 <78750000>;
128 opp-microvolt = <800000>;
131 opp-19687500 {
132 opp-hz = /bits/ 64 <19687500>;
133 opp-microvolt = <800000>;
138 compatible = "arm,psci-1.0", "arm,psci-0.2";
142 qextal_clk: qextal-clk {
143 compatible = "fixed-clock";
144 #clock-cells = <0>;
146 clock-frequency = <0>;
149 rtxin_clk: rtxin-clk {
150 compatible = "fixed-clock";
151 #clock-cells = <0>;
153 clock-frequency = <0>;
157 compatible = "simple-bus";
158 interrupt-parent = <&gic>;
159 #address-cells = <2>;
160 #size-cells = <2>;
163 icu: interrupt-controller@10400000 {
164 compatible = "renesas,r9a09g047-icu";
166 #interrupt-cells = <2>;
167 #address-cells = <0>;
168 interrupt-controller;
227 interrupt-names = "nmi",
242 "int-ca55-0", "int-ca55-1",
243 "int-ca55-2", "int-ca55-3",
244 "icu-error-ca55",
245 "gpt-u0-gtciada", "gpt-u0-gtciadb",
246 "gpt-u1-gtciada", "gpt-u1-gtciadb";
248 power-domains = <&cpg>;
253 compatible = "renesas,r9a09g047-pinctrl";
256 gpio-controller;
257 #gpio-cells = <2>;
258 gpio-ranges = <&pinctrl 0 0 232>;
259 #interrupt-cells = <2>;
260 interrupt-controller;
261 interrupt-parent = <&icu>;
262 power-domains = <&cpg>;
266 cpg: clock-controller@10420000 {
267 compatible = "renesas,r9a09g047-cpg";
270 clock-names = "audio_extal", "rtxin", "qextal";
271 #clock-cells = <2>;
272 #reset-cells = <1>;
273 #power-domain-cells = <0>;
276 sys: system-controller@10430000 {
277 compatible = "renesas,r9a09g047-sys";
284 compatible = "renesas,r9a09g047-xspi";
287 reg-names = "regs", "dirmap";
290 interrupt-names = "pulse", "err_pulse";
295 clock-names = "ahb", "axi", "spi", "spix2";
297 reset-names = "hresetn", "aresetn";
298 power-domains = <&cpg>;
299 #address-cells = <1>;
300 #size-cells = <0>;
301 status = "disabled";
305 compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057";
316 interrupt-names = "eri", "rxi", "txi", "bri", "dri",
317 "tei", "tei-dri", "rxi-edge", "txi-edge";
319 clock-names = "fck";
320 power-domains = <&cpg>;
322 status = "disabled";
326 compatible = "renesas,r9a09g047-canfd";
348 interrupt-names = "g_err", "g_recc",
357 clock-names = "fck", "ram_clk", "can_clk";
358 assigned-clocks = <&cpg CPG_MOD 0x9e>;
359 assigned-clock-rates = <80000000>;
361 reset-names = "rstp_n", "rstc_n";
362 power-domains = <&cpg>;
363 status = "disabled";
366 status = "disabled";
369 status = "disabled";
372 status = "disabled";
375 status = "disabled";
378 status = "disabled";
381 status = "disabled";
386 compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt";
389 clock-names = "pclk", "oscclk";
391 power-domains = <&cpg>;
392 status = "disabled";
396 compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt";
399 clock-names = "pclk", "oscclk";
401 power-domains = <&cpg>;
402 status = "disabled";
406 compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt";
409 clock-names = "pclk", "oscclk";
411 power-domains = <&cpg>;
412 status = "disabled";
416 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
426 interrupt-names = "tei", "ri", "ti", "spi", "sti",
430 power-domains = <&cpg>;
431 #address-cells = <1>;
432 #size-cells = <0>;
433 status = "disabled";
437 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
447 interrupt-names = "tei", "ri", "ti", "spi", "sti",
451 power-domains = <&cpg>;
452 #address-cells = <1>;
453 #size-cells = <0>;
454 status = "disabled";
458 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
468 interrupt-names = "tei", "ri", "ti", "spi", "sti",
472 power-domains = <&cpg>;
473 #address-cells = <1>;
474 #size-cells = <0>;
475 status = "disabled";
479 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
489 interrupt-names = "tei", "ri", "ti", "spi", "sti",
493 power-domains = <&cpg>;
494 #address-cells = <1>;
495 #size-cells = <0>;
496 status = "disabled";
500 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
510 interrupt-names = "tei", "ri", "ti", "spi", "sti",
514 power-domains = <&cpg>;
515 #address-cells = <1>;
516 #size-cells = <0>;
517 status = "disabled";
521 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
531 interrupt-names = "tei", "ri", "ti", "spi", "sti",
535 power-domains = <&cpg>;
536 #address-cells = <1>;
537 #size-cells = <0>;
538 status = "disabled";
542 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
552 interrupt-names = "tei", "ri", "ti", "spi", "sti",
556 power-domains = <&cpg>;
557 #address-cells = <1>;
558 #size-cells = <0>;
559 status = "disabled";
563 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
573 interrupt-names = "tei", "ri", "ti", "spi", "sti",
577 power-domains = <&cpg>;
578 #address-cells = <1>;
579 #size-cells = <0>;
580 status = "disabled";
584 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
594 interrupt-names = "tei", "ri", "ti", "spi", "sti",
598 power-domains = <&cpg>;
599 #address-cells = <1>;
600 #size-cells = <0>;
601 status = "disabled";
605 compatible = "renesas,r9a09g047-mali",
606 "arm,mali-bifrost";
612 interrupt-names = "job", "mmu", "gpu", "event";
616 clock-names = "gpu", "bus", "bus_ace";
617 power-domains = <&cpg>;
619 reset-names = "rst", "axi_rst", "ace_rst";
620 operating-points-v2 = <&gpu_opp_table>;
621 status = "disabled";
624 gic: interrupt-controller@14900000 {
625 compatible = "arm,gic-v3";
628 #interrupt-cells = <3>;
629 #address-cells = <0>;
630 interrupt-controller;
635 compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057";
641 clock-names = "core", "clkh", "cd", "aclk";
643 power-domains = <&cpg>;
644 status = "disabled";
646 sdhi0_vqmmc: vqmmc-regulator {
647 regulator-name = "SDHI0-VQMMC";
648 regulator-min-microvolt = <1800000>;
649 regulator-max-microvolt = <3300000>;
650 status = "disabled";
655 compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057";
661 clock-names = "core", "clkh", "cd", "aclk";
663 power-domains = <&cpg>;
664 status = "disabled";
666 sdhi1_vqmmc: vqmmc-regulator {
667 regulator-name = "SDHI1-VQMMC";
668 regulator-min-microvolt = <1800000>;
669 regulator-max-microvolt = <3300000>;
670 status = "disabled";
675 compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057";
681 clock-names = "core", "clkh", "cd", "aclk";
683 power-domains = <&cpg>;
684 status = "disabled";
686 sdhi2_vqmmc: vqmmc-regulator {
687 regulator-name = "SDHI2-VQMMC";
688 regulator-min-microvolt = <1800000>;
689 regulator-max-microvolt = <3300000>;
690 status = "disabled";
695 compatible = "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth",
696 "snps,dwmac-5.20";
702 clock-names = "stmmaceth", "pclk", "ptp_ref",
703 "tx", "rx", "tx-180", "rx-180";
715 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
716 "rx-queue-0", "rx-queue-1", "rx-queue-2",
717 "rx-queue-3", "tx-queue-0", "tx-queue-1",
718 "tx-queue-2", "tx-queue-3";
720 power-domains = <&cpg>;
721 snps,multicast-filter-bins = <256>;
722 snps,perfect-filter-entries = <128>;
723 rx-fifo-depth = <8192>;
724 tx-fifo-depth = <8192>;
725 snps,fixed-burst;
726 snps,no-pbl-x8;
728 snps,axi-config = <&stmmac_axi_setup>;
729 snps,mtl-rx-config = <&mtl_rx_setup0>;
730 snps,mtl-tx-config = <&mtl_tx_setup0>;
733 status = "disabled";
736 compatible = "snps,dwmac-mdio";
737 #address-cells = <1>;
738 #size-cells = <0>;
741 mtl_rx_setup0: rx-queues-config {
742 snps,rx-queues-to-use = <4>;
743 snps,rx-sched-sp;
746 snps,dcb-algorithm;
748 snps,map-to-dma-channel = <0>;
752 snps,dcb-algorithm;
754 snps,map-to-dma-channel = <1>;
758 snps,dcb-algorithm;
760 snps,map-to-dma-channel = <2>;
764 snps,dcb-algorithm;
766 snps,map-to-dma-channel = <3>;
770 mtl_tx_setup0: tx-queues-config {
771 snps,tx-queues-to-use = <4>;
774 snps,dcb-algorithm;
779 snps,dcb-algorithm;
784 snps,dcb-algorithm;
789 snps,dcb-algorithm;
796 compatible = "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth",
797 "snps,dwmac-5.20";
803 clock-names = "stmmaceth", "pclk", "ptp_ref",
804 "tx", "rx", "tx-180", "rx-180";
816 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
817 "rx-queue-0", "rx-queue-1", "rx-queue-2",
818 "rx-queue-3", "tx-queue-0", "tx-queue-1",
819 "tx-queue-2", "tx-queue-3";
821 power-domains = <&cpg>;
822 snps,multicast-filter-bins = <256>;
823 snps,perfect-filter-entries = <128>;
824 rx-fifo-depth = <8192>;
825 tx-fifo-depth = <8192>;
826 snps,fixed-burst;
827 snps,no-pbl-x8;
829 snps,axi-config = <&stmmac_axi_setup>;
830 snps,mtl-rx-config = <&mtl_rx_setup1>;
831 snps,mtl-tx-config = <&mtl_tx_setup1>;
834 status = "disabled";
837 compatible = "snps,dwmac-mdio";
838 #address-cells = <1>;
839 #size-cells = <0>;
842 mtl_rx_setup1: rx-queues-config {
843 snps,rx-queues-to-use = <4>;
844 snps,rx-sched-sp;
847 snps,dcb-algorithm;
849 snps,map-to-dma-channel = <0>;
853 snps,dcb-algorithm;
855 snps,map-to-dma-channel = <1>;
859 snps,dcb-algorithm;
861 snps,map-to-dma-channel = <2>;
865 snps,dcb-algorithm;
867 snps,map-to-dma-channel = <3>;
871 mtl_tx_setup1: tx-queues-config {
872 snps,tx-queues-to-use = <4>;
875 snps,dcb-algorithm;
880 snps,dcb-algorithm;
885 snps,dcb-algorithm;
890 snps,dcb-algorithm;
897 compatible = "renesas,r9a09g047-cru";
902 clock-names = "video", "apb", "axi";
908 interrupt-names = "image_conv", "axi_mst_err",
912 reset-names = "presetn", "aresetn";
913 power-domains = <&cpg>;
914 status = "disabled";
916 ports {
917 #address-cells = <1>;
918 #size-cells = <0>;
921 #address-cells = <1>;
922 #size-cells = <0>;
927 remote-endpoint = <&csi2cru>;
934 compatible = "renesas,r9a09g047-csi2", "renesas,r9a09g057-csi2";
938 clock-names = "video", "apb";
940 reset-names = "presetn", "cmn-rstb";
941 power-domains = <&cpg>;
942 status = "disabled";
944 ports {
945 #address-cells = <1>;
946 #size-cells = <0>;
953 #address-cells = <1>;
954 #size-cells = <0>;
959 remote-endpoint = <&crucsi2>;
966 stmmac_axi_setup: stmmac-axi-config {
974 compatible = "arm,armv8-timer";
975 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
980 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";