dts/renesas/r9a09g047.dtsi

18 		#clock-cells = <0>;
20 		clock-frequency = <0>;
30 	cluster0_opp: opp-table-0 {
58 		#size-cells = <0>;
60 		cpu0: cpu@0 {
62 			reg = <0>;
72 			reg = <0x100>;
82 			reg = <0x200>;
92 			reg = <0x300>;
100 		L3_CA55: cache-controller-0 {
103 			cache-size = <0x100000>;
144 		#clock-cells = <0>;
146 		clock-frequency = <0>;
151 		#clock-cells = <0>;
153 		clock-frequency = <0>;
165 			reg = <0 0x10400000 0 0x10000>;
167 			#address-cells = <0>;
169 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
242 					  "int-ca55-0", "int-ca55-1",
247 			clocks = <&cpg CPG_MOD 0x5>;
249 			resets = <&cpg 0x36>;
254 			reg = <0 0x10410000 0 0x10000>;
258 			gpio-ranges = <&pinctrl 0 0 232>;
263 			resets = <&cpg 0xa5>, <&cpg 0xa6>;
268 			reg = <0 0x10420000 0 0x10000>;
273 			#power-domain-cells = <0>;
278 			reg = <0 0x10430000 0 0x10000>;
280 			resets = <&cpg 0x30>;
285 			reg = <0 0x11030000 0 0x10000>,
286 			      <0 0x20000000 0 0x10000000>;
291 			clocks = <&cpg CPG_MOD 0x9f>,
292 				 <&cpg CPG_MOD 0xa0>,
294 				 <&cpg CPG_MOD 0xa1>;
296 			resets = <&cpg 0xa3>, <&cpg 0xa4>;
300 			#size-cells = <0>;
306 			reg = <0 0x11c01400 0 0x400>;
318 			clocks = <&cpg CPG_MOD 0x8f>;
321 			resets = <&cpg 0x95>;
327 			reg = <0 0x12440000 0 0x40000>;
355 			clocks = <&cpg CPG_MOD 0x9c>, <&cpg CPG_MOD 0x9d>,
356 				 <&cpg CPG_MOD 0x9e>;
358 			assigned-clocks = <&cpg CPG_MOD 0x9e>;
360 			resets = <&cpg 0xa1>, <&cpg 0xa2>;
387 			reg = <0 0x14400000 0 0x400>;
388 			clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>;
390 			resets = <&cpg 0x76>;
397 			reg = <0 0x13000000 0 0x400>;
398 			clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>;
400 			resets = <&cpg 0x77>;
407 			reg = <0 0x13000400 0 0x400>;
408 			clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>;
410 			resets = <&cpg 0x78>;
417 			reg = <0 0x14400400 0 0x400>;
428 			clocks = <&cpg CPG_MOD 0x94>;
429 			resets = <&cpg 0x98>;
432 			#size-cells = <0>;
438 			reg = <0 0x14400800 0 0x400>;
449 			clocks = <&cpg CPG_MOD 0x95>;
450 			resets = <&cpg 0x99>;
453 			#size-cells = <0>;
459 			reg = <0 0x14400c00 0 0x400>;
470 			clocks = <&cpg CPG_MOD 0x96>;
471 			resets = <&cpg 0x9a>;
474 			#size-cells = <0>;
480 			reg = <0 0x14401000 0 0x400>;
491 			clocks = <&cpg CPG_MOD 0x97>;
492 			resets = <&cpg 0x9b>;
495 			#size-cells = <0>;
501 			reg = <0 0x14401400 0 0x400>;
512 			clocks = <&cpg CPG_MOD 0x98>;
513 			resets = <&cpg 0x9c>;
516 			#size-cells = <0>;
522 			reg = <0 0x14401800 0 0x400>;
533 			clocks = <&cpg CPG_MOD 0x99>;
534 			resets = <&cpg 0x9d>;
537 			#size-cells = <0>;
543 			reg = <0 0x14401c00 0 0x400>;
554 			clocks = <&cpg CPG_MOD 0x9a>;
555 			resets = <&cpg 0x9e>;
558 			#size-cells = <0>;
564 			reg = <0 0x14402000 0 0x400>;
575 			clocks = <&cpg CPG_MOD 0x9b>;
576 			resets = <&cpg 0x9f>;
579 			#size-cells = <0>;
585 			reg = <0 0x11c01000 0 0x400>;
596 			clocks = <&cpg CPG_MOD 0x93>;
597 			resets = <&cpg 0xa0>;
600 			#size-cells = <0>;
607 			reg = <0x0 0x14850000 0x0 0x10000>;
613 			clocks = <&cpg CPG_MOD 0xf0>,
614 				 <&cpg CPG_MOD 0xf1>,
615 				 <&cpg CPG_MOD 0xf2>;
618 			resets = <&cpg 0xdd>, <&cpg 0xde>, <&cpg 0xdf>;
626 			reg = <0x0 0x14900000 0 0x20000>,
627 			      <0x0 0x14940000 0 0x80000>;
629 			#address-cells = <0>;
636 			reg = <0x0 0x15c00000 0 0x10000>;
639 			clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>,
640 				 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>;
642 			resets = <&cpg 0xa7>;
656 			reg = <0x0 0x15c10000 0 0x10000>;
659 			clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>,
660 				 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>;
662 			resets = <&cpg 0xa8>;
676 			reg = <0x0 0x15c20000 0 0x10000>;
679 			clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>,
680 				 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>;
682 			resets = <&cpg 0xa9>;
697 			reg = <0 0x15c30000 0 0x10000>;
698 			clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>,
700 				 <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>,
701 				 <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>;
716 					  "rx-queue-0", "rx-queue-1", "rx-queue-2",
717 					  "rx-queue-3", "tx-queue-0", "tx-queue-1",
719 			resets = <&cpg 0xb0>;
738 				#size-cells = <0>;
747 					snps,priority = <0x1>;
748 					snps,map-to-dma-channel = <0>;
753 					snps,priority = <0x2>;
759 					snps,priority = <0x4>;
765 					snps,priority = <0x8>;
775 					snps,priority = <0x1>;
780 					snps,priority = <0x2>;
785 					snps,priority = <0x4>;
790 					snps,priority = <0x8>;
798 			reg = <0 0x15c40000 0 0x10000>;
799 			clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>,
801 				 <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>,
802 				 <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>;
817 					  "rx-queue-0", "rx-queue-1", "rx-queue-2",
818 					  "rx-queue-3", "tx-queue-0", "tx-queue-1",
820 			resets = <&cpg 0xb1>;
839 				#size-cells = <0>;
848 					snps,priority = <0x1>;
849 					snps,map-to-dma-channel = <0>;
854 					snps,priority = <0x2>;
860 					snps,priority = <0x4>;
866 					snps,priority = <0x8>;
876 					snps,priority = <0x1>;
881 					snps,priority = <0x2>;
886 					snps,priority = <0x4>;
891 					snps,priority = <0x8>;
898 			reg = <0 0x16000000 0 0x400>;
899 			clocks = <&cpg CPG_MOD 0xd3>,
900 				 <&cpg CPG_MOD 0xd4>,
901 				 <&cpg CPG_MOD 0xd2>;
911 			resets = <&cpg 0xc5>, <&cpg 0xc6>;
918 				#size-cells = <0>;
922 					#size-cells = <0>;
925 					crucsi2: endpoint@0 {
926 						reg = <0>;
935 			reg = <0 0x16000400 0 0xc00>;
937 			clocks = <&cpg CPG_MOD 0xd3>, <&cpg CPG_MOD 0xd4>;
939 			resets = <&cpg 0xc5>, <&cpg 0xc7>;
946 				#size-cells = <0>;
948 				port@0 {
949 					reg = <0>;
954 					#size-cells = <0>;
957 					csi2cru: endpoint@0 {
958 						reg = <0>;
968 		snps,wr_osr_lmt = <0xf>;
969 		snps,rd_osr_lmt = <0xf>;
970 		snps,blen = <16 8 4 0 0 0 0>;