Lines Matching full:cpg
9 #include <dt-bindings/clock/r9a07g044-cpg.h>
94 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
104 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
240 clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
241 power-domains = <&cpg>;
242 resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
356 clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
357 resets = <&cpg R9A07G044_GPT_RST_C>;
358 power-domains = <&cpg>;
370 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
371 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
374 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
377 power-domains = <&cpg>;
390 clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
391 <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
394 resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;
397 power-domains = <&cpg>;
409 clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,
410 <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,
413 resets = <&cpg R9A07G044_SSI2_RST_M2_REG>;
416 power-domains = <&cpg>;
429 clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,
430 <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,
433 resets = <&cpg R9A07G044_SSI3_RST_M2_REG>;
436 power-domains = <&cpg>;
448 clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>;
449 resets = <&cpg R9A07G044_RSPI0_RST>;
452 power-domains = <&cpg>;
466 clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>;
467 resets = <&cpg R9A07G044_RSPI1_RST>;
470 power-domains = <&cpg>;
484 clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>;
485 resets = <&cpg R9A07G044_RSPI2_RST>;
488 power-domains = <&cpg>;
506 clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
508 power-domains = <&cpg>;
509 resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
524 clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>;
526 power-domains = <&cpg>;
527 resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>;
542 clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>;
544 power-domains = <&cpg>;
545 resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>;
560 clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>;
562 power-domains = <&cpg>;
563 resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>;
578 clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>;
580 power-domains = <&cpg>;
581 resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>;
593 clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
595 power-domains = <&cpg>;
596 resets = <&cpg R9A07G044_SCI0_RST>;
608 clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>;
610 power-domains = <&cpg>;
611 resets = <&cpg R9A07G044_SCI1_RST>;
629 clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
630 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
633 assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
635 resets = <&cpg R9A07G044_CANFD_RSTP_N>,
636 <&cpg R9A07G044_CANFD_RSTC_N>;
638 power-domains = <&cpg>;
664 clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>;
666 resets = <&cpg R9A07G044_I2C0_MRST>;
667 power-domains = <&cpg>;
686 clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>;
688 resets = <&cpg R9A07G044_I2C1_MRST>;
689 power-domains = <&cpg>;
708 clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>;
710 resets = <&cpg R9A07G044_I2C2_MRST>;
711 power-domains = <&cpg>;
730 clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>;
732 resets = <&cpg R9A07G044_I2C3_MRST>;
733 power-domains = <&cpg>;
741 clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
742 <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
744 resets = <&cpg R9A07G044_ADC_PRESETN>,
745 <&cpg R9A07G044_ADC_ADRST_N>;
747 power-domains = <&cpg>;
783 clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>;
784 resets = <&cpg R9A07G044_TSU_PRESETN>;
785 power-domains = <&cpg>;
797 clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>,
798 <&cpg CPG_MOD R9A07G044_SPI_CLK>;
799 resets = <&cpg R9A07G044_SPI_RST>;
800 power-domains = <&cpg>;
809 clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
810 <&cpg CPG_MOD R9A07G044_CRU_PCLK>,
811 <&cpg CPG_MOD R9A07G044_CRU_ACLK>;
817 resets = <&cpg R9A07G044_CRU_PRESETN>,
818 <&cpg R9A07G044_CRU_ARESETN>;
820 power-domains = <&cpg>;
854 clocks = <&cpg CPG_MOD R9A07G044_CRU_SYSCLK>,
855 <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
856 <&cpg CPG_MOD R9A07G044_CRU_PCLK>;
858 resets = <&cpg R9A07G044_CRU_PRESETN>,
859 <&cpg R9A07G044_CRU_CMN_RSTB>;
861 power-domains = <&cpg>;
898 clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
899 <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
900 <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
901 <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
902 <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
903 <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
905 resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
906 <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
907 <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
909 power-domains = <&cpg>;
933 clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
934 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
935 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
937 power-domains = <&cpg>;
938 resets = <&cpg R9A07G044_LCDC_RESET_N>;
946 clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
947 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
948 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
950 power-domains = <&cpg>;
951 resets = <&cpg R9A07G044_LCDC_RESET_N>;
958 clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
959 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
960 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
962 power-domains = <&cpg>;
963 resets = <&cpg R9A07G044_LCDC_RESET_N>;
984 cpg: clock-controller@11010000 {
985 compatible = "renesas,r9a07g044-cpg";
1015 clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
1016 power-domains = <&cpg>;
1017 resets = <&cpg R9A07G044_GPIO_RSTN>,
1018 <&cpg R9A07G044_GPIO_PORT_RESETN>,
1019 <&cpg R9A07G044_GPIO_SPARE_RESETN>;
1090 clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
1091 <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
1093 power-domains = <&cpg>;
1094 resets = <&cpg R9A07G044_IA55_RESETN>;
1124 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
1125 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
1127 power-domains = <&cpg>;
1128 resets = <&cpg R9A07G044_DMAC_ARESETN>,
1129 <&cpg R9A07G044_DMAC_RST_ASYNC>;
1144 clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>,
1145 <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>,
1146 <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>;
1148 power-domains = <&cpg>;
1149 resets = <&cpg R9A07G044_GPU_RESETN>,
1150 <&cpg R9A07G044_GPU_AXI_RESETN>,
1151 <&cpg R9A07G044_GPU_ACE_RESETN>;
1172 clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
1173 <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
1174 <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
1175 <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
1177 resets = <&cpg R9A07G044_SDHI0_IXRST>;
1178 power-domains = <&cpg>;
1188 clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
1189 <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
1190 <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
1191 <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
1193 resets = <&cpg R9A07G044_SDHI1_IXRST>;
1194 power-domains = <&cpg>;
1207 clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>,
1208 <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>,
1209 <&cpg CPG_CORE R9A07G044_CLK_HP>;
1211 resets = <&cpg R9A07G044_ETH0_RST_HW_N>;
1212 power-domains = <&cpg>;
1227 clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>,
1228 <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>,
1229 <&cpg CPG_CORE R9A07G044_CLK_HP>;
1231 resets = <&cpg R9A07G044_ETH1_RST_HW_N>;
1232 power-domains = <&cpg>;
1242 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
1243 resets = <&cpg R9A07G044_USB_PRESETN>;
1244 power-domains = <&cpg>;
1257 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1258 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
1260 <&cpg R9A07G044_USB_U2H0_HRESETN>;
1263 power-domains = <&cpg>;
1271 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1272 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
1274 <&cpg R9A07G044_USB_U2H1_HRESETN>;
1277 power-domains = <&cpg>;
1285 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1286 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
1288 <&cpg R9A07G044_USB_U2H0_HRESETN>;
1292 power-domains = <&cpg>;
1300 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1301 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
1303 <&cpg R9A07G044_USB_U2H1_HRESETN>;
1307 power-domains = <&cpg>;
1316 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1317 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
1320 power-domains = <&cpg>;
1329 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1330 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
1333 power-domains = <&cpg>;
1345 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1346 <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
1348 <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
1352 power-domains = <&cpg>;
1360 clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>,
1361 <&cpg CPG_MOD R9A07G044_WDT0_CLK>;
1366 resets = <&cpg R9A07G044_WDT0_PRESETN>;
1367 power-domains = <&cpg>;
1375 clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>,
1376 <&cpg CPG_MOD R9A07G044_WDT1_CLK>;
1381 resets = <&cpg R9A07G044_WDT1_PRESETN>;
1382 power-domains = <&cpg>;
1391 clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>;
1392 resets = <&cpg R9A07G044_OSTM0_PRESETZ>;
1393 power-domains = <&cpg>;
1402 clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>;
1403 resets = <&cpg R9A07G044_OSTM1_PRESETZ>;
1404 power-domains = <&cpg>;
1413 clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>;
1414 resets = <&cpg R9A07G044_OSTM2_PRESETZ>;
1415 power-domains = <&cpg>;