Lines Matching full:cpg
9 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
34 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
44 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
54 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
64 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
136 clocks = <&cpg CPG_MOD 402>;
138 resets = <&cpg 402>;
152 clocks = <&cpg CPG_MOD 912>;
154 resets = <&cpg 912>;
167 clocks = <&cpg CPG_MOD 911>;
169 resets = <&cpg 911>;
182 clocks = <&cpg CPG_MOD 910>;
184 resets = <&cpg 910>;
197 clocks = <&cpg CPG_MOD 909>;
199 resets = <&cpg 909>;
212 clocks = <&cpg CPG_MOD 908>;
214 resets = <&cpg 908>;
227 clocks = <&cpg CPG_MOD 907>;
229 resets = <&cpg 907>;
244 clocks = <&cpg CPG_MOD 303>;
247 resets = <&cpg 303>;
263 clocks = <&cpg CPG_MOD 302>;
266 resets = <&cpg 302>;
282 clocks = <&cpg CPG_MOD 301>;
285 resets = <&cpg 301>;
301 clocks = <&cpg CPG_MOD 300>;
304 resets = <&cpg 300>;
308 cpg: clock-controller@e6150000 {
309 compatible = "renesas,r8a77980-cpg-mssr";
338 clocks = <&cpg CPG_MOD 522>;
340 resets = <&cpg 522>;
355 clocks = <&cpg CPG_MOD 407>;
357 resets = <&cpg 407>;
367 clocks = <&cpg CPG_MOD 125>;
370 resets = <&cpg 125>;
382 clocks = <&cpg CPG_MOD 124>;
385 resets = <&cpg 124>;
397 clocks = <&cpg CPG_MOD 123>;
400 resets = <&cpg 123>;
412 clocks = <&cpg CPG_MOD 122>;
415 resets = <&cpg 122>;
427 clocks = <&cpg CPG_MOD 121>;
430 resets = <&cpg 121>;
439 clocks = <&cpg CPG_MOD 931>;
441 resets = <&cpg 931>;
456 clocks = <&cpg CPG_MOD 930>;
458 resets = <&cpg 930>;
473 clocks = <&cpg CPG_MOD 929>;
475 resets = <&cpg 929>;
490 clocks = <&cpg CPG_MOD 928>;
492 resets = <&cpg 928>;
504 clocks = <&cpg CPG_MOD 927>;
506 resets = <&cpg 927>;
518 clocks = <&cpg CPG_MOD 919>;
520 resets = <&cpg 919>;
536 clocks = <&cpg CPG_MOD 520>,
537 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
544 resets = <&cpg 520>;
554 clocks = <&cpg CPG_MOD 519>,
555 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
562 resets = <&cpg 519>;
572 clocks = <&cpg CPG_MOD 518>,
573 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
580 resets = <&cpg 518>;
590 clocks = <&cpg CPG_MOD 517>,
591 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
598 resets = <&cpg 517>;
606 clocks = <&cpg CPG_MOD 319>;
608 resets = <&cpg 319>;
619 clocks = <&cpg CPG_MOD 914>,
620 <&cpg CPG_CORE R8A77980_CLK_CANFD>,
623 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
626 resets = <&cpg 914>;
674 clocks = <&cpg CPG_MOD 812>;
677 resets = <&cpg 812>;
691 clocks = <&cpg CPG_MOD 523>;
693 resets = <&cpg 523>;
701 clocks = <&cpg CPG_MOD 523>;
703 resets = <&cpg 523>;
711 clocks = <&cpg CPG_MOD 523>;
713 resets = <&cpg 523>;
721 clocks = <&cpg CPG_MOD 523>;
723 resets = <&cpg 523>;
731 clocks = <&cpg CPG_MOD 523>;
733 resets = <&cpg 523>;
743 clocks = <&cpg CPG_MOD 207>,
744 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
751 resets = <&cpg 207>;
761 clocks = <&cpg CPG_MOD 206>,
762 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
769 resets = <&cpg 206>;
779 clocks = <&cpg CPG_MOD 204>,
780 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
787 resets = <&cpg 204>;
797 clocks = <&cpg CPG_MOD 203>,
798 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
805 resets = <&cpg 203>;
813 clocks = <&cpg CPG_MOD 304>;
815 resets = <&cpg 304>;
825 clocks = <&cpg CPG_MOD 211>;
827 resets = <&cpg 211>;
838 clocks = <&cpg CPG_MOD 210>;
840 resets = <&cpg 210>;
851 clocks = <&cpg CPG_MOD 209>;
853 resets = <&cpg 209>;
864 clocks = <&cpg CPG_MOD 208>;
866 resets = <&cpg 208>;
876 clocks = <&cpg CPG_MOD 811>;
878 resets = <&cpg 811>;
904 clocks = <&cpg CPG_MOD 810>;
908 resets = <&cpg 810>;
932 clocks = <&cpg CPG_MOD 809>;
934 resets = <&cpg 809>;
960 clocks = <&cpg CPG_MOD 808>;
962 resets = <&cpg 808>;
988 clocks = <&cpg CPG_MOD 807>;
990 resets = <&cpg 807>;
1016 clocks = <&cpg CPG_MOD 806>;
1018 resets = <&cpg 806>;
1044 clocks = <&cpg CPG_MOD 805>;
1046 resets = <&cpg 805>;
1072 clocks = <&cpg CPG_MOD 804>;
1074 resets = <&cpg 804>;
1100 clocks = <&cpg CPG_MOD 628>;
1102 resets = <&cpg 628>;
1111 clocks = <&cpg CPG_MOD 627>;
1113 resets = <&cpg 627>;
1122 clocks = <&cpg CPG_MOD 625>;
1124 resets = <&cpg 625>;
1133 clocks = <&cpg CPG_MOD 618>;
1135 resets = <&cpg 618>;
1144 clocks = <&cpg CPG_MOD 612>;
1146 resets = <&cpg 612>;
1155 clocks = <&cpg CPG_MOD 608>;
1157 resets = <&cpg 608>;
1166 clocks = <&cpg CPG_MOD 605>;
1168 resets = <&cpg 605>;
1177 clocks = <&cpg CPG_MOD 604>;
1179 resets = <&cpg 604>;
1210 clocks = <&cpg CPG_MOD 218>;
1213 resets = <&cpg 218>;
1252 clocks = <&cpg CPG_MOD 217>;
1255 resets = <&cpg 217>;
1272 clocks = <&cpg CPG_MOD 813>;
1274 resets = <&cpg 813>;
1351 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77980_CLK_SD0H>;
1354 resets = <&cpg 314>;
1368 clocks = <&cpg CPG_MOD 917>;
1370 resets = <&cpg 917>;
1387 clocks = <&cpg CPG_MOD 408>;
1390 resets = <&cpg 408>;
1413 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1416 resets = <&cpg 319>;
1428 clocks = <&cpg CPG_MOD 623>;
1430 resets = <&cpg 623>;
1437 clocks = <&cpg CPG_MOD 603>;
1439 resets = <&cpg 603>;
1447 clocks = <&cpg CPG_MOD 716>;
1449 resets = <&cpg 716>;
1490 clocks = <&cpg CPG_MOD 715>;
1492 resets = <&cpg 715>;
1533 clocks = <&cpg CPG_MOD 724>;
1536 resets = <&cpg 724>;
1562 clocks = <&cpg CPG_MOD 727>;
1564 resets = <&cpg 727>;